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LF to 2.7 GHz Dual 60 dB TruPwrTM Detector AD8364
FEATURES
RMS measurement of high crest-factor signals Dual-channel and channel difference outputs ports Integrated accurately scaled temperature sensor Wide dynamic range 1 dB over 60 dB 0.5 dB temperature-stable linear-in-dB response Low log conformance ripple +5 V operation at 70 mA, -40C to +85C Small footprint, 5 mm x 5 mm, LFCSP
FUNCTIONAL BLOCK DIAGRAM
ACOM ACOM
18
COMA
DECA
CHPA
TEMP
VPSR
24
23
22
21
20
19
17
TEMP VPSA 25 INHA 26 INLA 27 PWDN 28 CHANNEL A TruPwrTM
VGA CONTROL
ISIG2 ITGT2
CLPA
16 15 14 13 12 11 10 9
VSTA OUTA FBKA OUTP OUTN FBKB OUTB VSTB
APPLICATIONS
Wireless infrastructure power amplifier linearization/control Antenna VSWR monitor Gain and power control and measurement Transmitter signal strength indication (TSSI) Dual-channel wireless infrastructure radios
COMR 29 INLB 30 INHB 31 VPSB
32
OUTA OUTB
CHANNEL B TruPwrTM
ISIG2 ITGT2
BIAS
1 2 3
VGA CONTROL
4 5 6 7 8
05334-001
VLVL
CHPB
DECB
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The AD8364 is a true rms, responding, dual-channel RF power measurement subsystem for the precise measurement and control of signal power. The flexibility of the AD8364 allows communications systems, such as RF power amplifiers and radio transceiver AGC circuits, to be monitored and controlled with ease. Operating on a single 5 V supply, each channel is fully specified for operation up to 2.7 GHz over a dynamic range of 60 dB. The AD8364 provides accurately scaled, independent, rms outputs of both RF measurement channels. Difference output ports, which measure the difference between the two channels, are also available. The on-chip channel matching makes the rms channel difference outputs extremely stable with temperature and process variations. The device also includes a useful temperature sensor with an accurately scaled voltage proportional to temperature, specified over the device operating temperature range. The AD8364 can be used with input signals having rms values from -55 dBm to +5 dBm referred to 50 and large crest factors with no accuracy degradation. Integrated in the AD8364 are two matched AD8362 channels (see the AD8362 data sheet for more information) with improved temperature performance and reduced log conformance ripple. Enhancements include improved temperature performance and reduced log-conformance ripple compared to the AD8362. Onchip wide bandwidth output op amps are connected to accommodate flexible configurations that support many system solutions. The device can easily be configured to provide four rms measurements simultaneously. Linear-in-dB rms measurements are supplied at OUTA and OUTB, with conveniently scaled slopes of 50 mV/dB. The rms difference between OUTA and OUTB is available as differential or single-ended signals at OUTP and OUTN. An optional voltage applied to VLVL provides a common mode reference level to offset OUTP and OUTN above ground. The AD8364 is supplied in a 32-lead, 5 mm x 5 mm LFCSP, for the operating temperature of -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
COMB
CLPB
ADJB
ADJA
VREF
AD8364 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 General Description and Theory.................................................. 18 Square Law Detector and Amplitude Target .......................... 19 RF Input Interface ...................................................................... 19 Offset Compensation ................................................................. 19 Temperature Sensor Interface................................................... 20 VREF Interface ........................................................................... 20 Power-Down Interface............................................................... 20 VST[A, B] Interface.................................................................... 20 OUT[A, B, P, N] Outputs .......................................................... 21 Measurement Channel Difference Output Using OUT[P, N] ........................................................................ 22 Controller Mode ......................................................................... 22 RF Measurement Mode Basic Connections............................ 23 Controller Mode Basic Connections ....................................... 24 Constant Output Power Operation.......................................... 27 Gain-Stable Transmitter/Receiver............................................ 29 Temperature Compensation Adjustment................................ 31 Device Calibration and Error Calculation.............................. 31 Selecting Calibration Points to Improve Accuracy over a Reduced Range................................................................ 32 Altering the Slope....................................................................... 34 Channel Isolation ....................................................................... 35 Choosing the Right Value for CHP[A, B] and CLP[A, B].... 36 RF Burst Response Time ........................................................... 36 Single-Ended Input Operation ................................................. 36 Printed Circuit Board Considerations..................................... 37 Package Considerations............................................................. 37 Description of Characterization............................................... 38 Basis for Error Calculations ...................................................... 38 Evaluation and Characterization Circuit Board Layouts...... 40 Evaluation Boards........................................................................... 44 Assembly Drawings.................................................................... 46 Outline Dimensions ....................................................................... 47 Ordering Guide .......................................................................... 47
REVISION HISTORY
4/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 48
AD8364 SPECIFICATIONS
VS = VPSA = VPSB = VPSR = 5 V, TA = 25C, Channel A frequency = Channel B frequency, VLVL = VREF, VST[A, B] = OUT[A, B], OUT[P, N] = FBK[A, B], differential input via Balun, CW input f 2.7 GHz, unless otherwise noted. Table 1.
Parameter OVERALL FUNCTION Signal Input Interface Specified Frequency Range DC Common-Mode Voltage Signal Output Interface Wideband Noise MEASUREMENT MODE, 450 MHz OPERATION 1 dB Dynamic Range1 0.5 dB Dynamic Range1 Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Conditions Channel A and Channel B, CW sine wave input INH[A, B] (Pins 26, 31) INL[A, B] (Pins 27, 30) Min Typ Max Unit
LF 2.5 OUT[A, B] (Pins 15, 10) CLP[A, B] = 0.1F, fSPOT = 100 kHz, RF input = 2140 MHz, -40 dBm ADJA = ADJB = 0 V, error referred to best fit line using linear regression @ PINH[A, B] = -40 dBm and -20 dBm, TA = 25C, balun = M/A-Com ETK4-2T Pins OUT[A, B] -40C < TA < +85C Pins OUT[A, B], (Channel A/Channel B) -40C < TA < +85C, (Channel A/Channel B) 1 dB error 1 dB error 40
2.7
GHz V nV/Hz
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation2
Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm Deviation from OUT[A, B] @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm Deviation from OUTP to OUTN @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm, -25 dBm Baluns = Macom ETC1.6-4-2-3 (both channels) Freq separation = 1 kHz PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB INHA/INLA, INHB/INLB differential drive With recommended balun ADJA = ADJB = 0 V, error referred to best fit line using linear regression @ PINH[A, B] = -40 dBm and -20 dBm, TA = 25C, balun = Mini-Circuits(R) JTX-4-10T Pins OUT[A, B], (Channel A/Channel B) -40C < TA < +85C Pins OUT[A, B], (Channel A/Channel B) -40C < TA < +85C 1 dB error, (Channel A/Channel B) 1 dB error, (Channel A/Channel B)
69 65 62/59 50/52 12 -58 51.6 -59 2.53 0.99 -0.1, +0.2 -0.2, +0.3 -0.3, +0.4 0.25 0.2 0.2 71 54 54 210||0.1 -12
dB dB dB dB dBm dBm mV/dB dBm V V dB dB dB dB dB dB dB dB dB ||pF dB
Input Impedance Input Return Loss MEASUREMENT MODE, 880 MHz OPERATION 1 dB Dynamic Range1 0.5 dB Dynamic Range1 Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In Output Voltage--Low Power In
Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm
Rev. 0 | Page 3 of 48
66/57 58/40 62/54 20/20 8/0 -58/-57 51.6 -59.2 2.54 0.99
dB dB dB dB dBm dBm mV/dB dBm V V
AD8364
Parameter Temperature Sensitivity Conditions Deviation from OUT[A, B] @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm Deviation from OUTP to OUTN @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm, -25 dBm Baluns = Macom ETC1.6-4-2-3 (both channels) PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB INHA/INLA, INHB/INLB differential drive With recommended balun ADJA = ADJB = 0.75 V, error referred to best fit line using linear regression @ PINH[A, B] = -40 dBm and -20 dBm, TA = 25C, balun = Murata LDB181G8820C-110 Pins OUT[A, B], (Channel A/Channel B) -40C < TA < +85C Pins OUT[A, B], (Channel A/Channel B) -40C < TA < +85C 1 dB error, (Channel A/Channel B) 1 dB error Min Typ +0.5 +0.5 +0.5 +0.1, -0.2 +0.1, -0.2 +0.1, -0.2 64 35 35 200||0.3 -9 Max Unit dB dB dB dB dB dB dB dB dB ||pF dB
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation2 Input Impedance Input Return Loss MEASUREMENT MODE, 1880 MHz OPERATION 1 dB Dynamic Range1 0.5 dB Dynamic Range1 Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation2 Input Impedance Input Return Loss MEASUREMENT MODE, 2.14 GHz OPERATION 1 dB Dynamic Range1 0.5 dB Dynamic Range1 Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In
Pins OUT[A, B] @ PINH[A,B] = -10 dBm Pins OUT[A, B] @ PINH[A,B] = -40 dBm Deviation from OUT[A, B] @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm Deviation from OUTP to OUTN @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm, -25 dBm Baluns = Macom ETC1.6-4-2-3 (both channels) PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB INHA/INLA, INHB/INLB differential drive With recommended balun ADJA = ADJB = 1.02 V, error referred to best fit line using linear regression @ PINH[A, B] = -40 dBm and -20 dBm, TA = 25C, balun = Murata LDB212G1020C-001 Pins OUT[A, B], (Channel A/Channel B) -40C < TA < +85C Pins OUT[A, B], (Channel A/Channel B) -40C < TA < +85C 1 dB Error, (Channel A/Channel B) 1 dB Error, (Channel A/Channel B) Channel A/Channel B Channel A/Channel B Pins OUT[A, B] @ PINH[A, B] = -10 dBm
Rev. 0 | Page 4 of 48
69/61 60/50 62/51 58/51 11/3 -58 50 -62 2.49 0.98 +0.5, -0.2 +0.5, -0.2 +0.5, -0.2 0.3 0.3 0.3 61 33 33 167||0.14 -8
dB dB dB dB dBm dBm mV/dB dBm V V dB dB dB dB dB dB dB dB dB ||pF dB
66/57 58/40 62/54 30/30 -2/-4 -57-51 49.5/52.1 -58.3/-57.1 2.42
dB dB dB dB dBm dBm mV/dB dBm V
AD8364
Parameter Output Voltage--Low Power In Temperature Sensitivity Conditions Pins OUT[A, B] @ PINH[A, B] = -40 dBm Deviation from OUT[A, B] @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm Deviation from OUTP to OUTN @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm, -25 dBm 5.5 dB peak-to-rms ratio (WCDMA one channel) 12 dB peak-to-rms ratio (WCDMA three channels) 18 dB peak-to-rms ratio (WCDMA four channels) Baluns = Macom ETC1.6-4-2-3 (both channels) PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB INHA/INLA, INHB/INLB differential drive With recommended balun ADJA = ADJB = 1.14 V, error referred to best fit line using linear regression @ PINH[A, B] = -40 dBm and -20 dBm, TA = 25C, balun = Murata LDB182G4520C-110 Pins OUT[A, B], (Channel A/Channel B) -40C < TA < +85C Pins OUT[A, B], (Channel A/Channel B) -40C < TA < +85C 1 dB error, (Channel A/Channel B) 1 dB error Min Typ 0.90 +0.1, -0.4 +0.1, -0.4 +0.1, -0.4 +0.1, -0.4 +0.2, -0.2 +0.1, -0.2 0.2 0.3 0.3 58 33 33 150||1.9 -10 Max Unit V dB dB dB dB dB dB dB dB dB dB dB dB ||pF dB
Deviation from CW Response
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation2 Input Impedance Input Return Loss MEASUREMENT MODE, 2.5 GHz OPERATION 1 dB Dynamic Range1 0.5 dB Dynamic Range1 Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity
Input A to Input B Isolation Input A to OUTB Isolation Input B to OUTA Isolation2 Input Impedance Input Return Loss OUTPUT INTERFACE Voltage Range Min Voltage Range Max Source/Sink Current
Pins OUT[A, B] @ PINH[A, B] = -10 dBm Pins OUT[A, B] @ PINH[A, B] = -40 dBm Deviation from OUT[A, B] @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm Deviation from OUTP to OUTN @ 25C -40C < TA < 85C; PINH[A, B] = -10 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -25 dBm, -25 dBm -40C < TA < 85C; PINH[A, B] = -40 dBm, -25 dBm Baluns = Macom ETC1.6-4-2-3 (both channels) PINHB = -50 dBm, OUTB = OUTBPINHB 1 dB PINHA = -50 dBm, OUTA = OUTAPINHA 1 dB INHA/INLA, INHB/INLB differential drive With recommended balun Pin OUTA and OUTB RL 200 to ground RL 200 to ground OUTA and OUTB held at VS/2, to 1% change
69/63 58 55/50 25 17/11 -52 50 -52.7 2.14 0.65 0.5 0.5 0.5 0.3 0.3 0.3 54 31 31 150||1.7 -11.5 0.09 VS - 0.15 70
dB dB dB dB dBm dBm mV/dB dBm V V dB dB dB dB dB dB dB dB ||pF dB V V mA
Rev. 0 | Page 5 of 48
AD8364
Parameter SETPOINT INPUT Voltage Range Input Resistance Logarithmic Scale Factor Logarithmic Intercept CHANNEL DIFFERENCE OUTPUT Voltage Range Min Voltage Range Max Source/Sink Current DIFFERENCE LEVEL ADJUST Voltage Range3 OUT[P,N] Voltage Range Input Resistance TEMPERATURE COMPENSATION Input Voltage Range Input Resistance VOLTAGE REFERENCE Output Voltage Temperature Sensitivity Current Limit Source/Sink TEMPERATURE REFERENCE Output Voltage Temperature Coefficient Current Source/Sink POWER-DOWN INTERFACE Logic Level to Enable Logic Level to Disable Input Current Enable Time Disable Time POWER INTERFACE Supply Voltage Quiescent Current Supply Current Conditions Pin VSTA and VSTB Law conformance error 1 dB f = 450 MHz, -40C TA +85C f = 450 MHz, -40C TA +85C, referred to 50 Pin OUTP and OUTN RL 200 to ground RL 200 to ground OUTP and OUTN held at VS/2, to 1% change Pin VLVL OUT[P, N] = FBK[A, B] OUT[P, N] = FBK[A, B] Min 0.5 68 50 -55 0.1 VS - 0.15 70 0 0 1 Pin ADJA and ADJB 0 >1 Pin VREF RF in = -55 dBm -40C TA +85C 1% change Pin TEMP TA = 25C, RL 10 k -40C TA +85C, RL 10 k TA = 25C to 1% change Pin PWDN Logic LO enables Logic HI disables Logic HI PWDN = 5 V Logic LO PWDN = 0 V PWDN LO to OUTA/OUTB at 100% final value, CLPA/B = Open, CHPA/B = 10 nF, RF in = 0 dBm PWDN HI to OUTA/OUTB at 10% final value, CLPA/B = Open, CHPA/B = 10nF, RF in = 0 dBm Pin VPS[A, B], VPSR RF in = -55 dBm, VS = 5 V -40C TA +85C PWDN enabled, VS = 5 V -40C TA +85C 2.5 0.4 10/3 0.62 2 1.6/2 1 3 95 <100 2 1.6 2.5 V M V mV/C mA V mV/C mA V V A A s s 5 VS - 0.15 Typ Max 3.75 Unit V k mV/dB dBm V V mA V V k
4.5 70
5.5 90 500 900
V mA mA A A
1 2 3
Best fit line, linear regression. See Figure 75 for a plot of isolation vs. frequency for a 1 dB error. VLVL + OUTA/2 should not exceed VPSA - 1.31 V. Likewise, VLVL + OUTB/2 should not exceed VPSB - 1.31 V.
Rev. 0 | Page 6 of 48
AD8364 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage VPSA, VPSB, VPSR PWDN, VSTA, VSTB, ADJA, ADJB, FBKA, FBKB Input Power (Referred to 50 ) Internal Power Dissipation JA JC JB JT Maximum Junction Temperature Operating Temperature Range Storage Temperature Range
1 2
Rating 5.5 V 0 V, 5.5 V 23 dBm 600 mW 39.8C/W1, 2 3.9C/W2 22.8C/W2 0.4C/W1, 2 125C -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Still air. All values are modeled using a standard 4-layer JEDEC test board with the pad soldered to the board and thermal vias in the board.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 48
AD8364 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 CHPA 23 DECA 22 COMA 21 VPSR 20 ACOM 19 TEMP 18 ACOM 17 CLPA
VPSA 25 INHA 26 INLA 27 PWDN 28 COMR 29 INLB 30 INHB 31 VPSB 32
AD8364
TOP VIEW
PIN 1 INDICATOR
16 VSTA 15 OUTA 14 FBKA 13 OUTP 12 OUTN 11 FBKB 10 OUTB 9 VSTB
1 2 3 4 5 6 7 8
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2, 23 3, 22, 29 4, 5 Mnemonic CHPB DECB, DECA COMB, COMA, COMR ADJB, ADJA Description Connect to common via a capacitor to determine 3 dB point of Channel B input signal highpass filter. Decoupling Terminals for INHA/INLA and INHB/INLB. Connect to common via a large capacitance to complete input circuit. Input System Common Connection. Connect via low impedance to system common. Temperature Compensation for Channel B and Channel A. An external voltage is connected to these pins to improve temperature drift. This voltage can be derived from VREF, that is, connect a resistor from VREF to ADJ[A, B] and another resistor from ADJ[A, B] to ground. The value of these resistors change as the frequency changes. General-Purpose Reference Voltage Output of 2.5 V. Reference Level Input for OUTP and OUTN. (Usually connected to VREF through a voltage divider or left open). Channel B and Channel A Connection for Loop Filter Integration (Averaging) Capacitor. Connect a ground-referenced capacitor to this pin. A resistor can be connected in series with this capacitor to improve loop stability and response time. The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel B that results in zero current flow in the loop integrating capacitor pin, CLPB. Channel B Output of Error Amplifier. In measurement mode, normally connected directly to VSTB. Feedback Through 1 k to the Negative Terminal of the Integrated Op Amp Driving OUTN. Channel Differencing Op Amp Output. In measurement mode, normally connected directly to FBKB and follows the equation OUTN = OUTA - OUTB + VLVL. Channel Differencing Op Amp Output. In measurement mode, normally connected directly to FBKA and follows the equation OUTP = OUTA - OUTB + VLVL. Feedback Through 1k to the Negative Terminal of the Integrated Op Amp Driving OUTP. Channel A Output of Error Amplifier. In measurement mode, normally connected directly to VSTA. The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel A that results in zero current flow in the loop integrating capacitor pin, CLPA. Analog Common for Channels A and B. Connect via low impedance to common. Supply for the Input System of Channels A and B. Supply for the internal references. Connect to +5 V power supply. Temperature Sensor Output. Connect to common via a capacitor to determine 3 dB point of Channel A input signal highpass filter. Channel A High and Low RF Signal Input Terminal. Disable/Enable Control Input. Apply logic high voltage to shut down the AD8364. Channel B Low and High RF Signal Input Terminal. The exposed paddle on the under side of the package should be soldered to a ground plane with low thermal and electrical characteristics.
Rev. 0 | Page 8 of 48
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
05334-002
Equiv. Circuit
Figure 52
Figure 68
6 7 8, 17
VREF VLVL CLPB, CLPA
Figure 54 Figure 58
9 10 11 12 13 14 15 16 18, 20 21, 25, 32 19 24 26, 27 28 30, 31 Under Package
VSTB OUTB FBKB OUTN OUTP FBKA OUTA VSTA ACOM VPSR, VPSA, VPSB TEMP CHPA INHA, INLA PWDN INLB, INHB Exposed Paddle
Figure 56 Figure 57
Figure 58 Figure 58
Figure 57 Figure 56
Figure 53
Figure 52 Figure 55 Figure 52
AD8364 TYPICAL PERFORMANCE CHARACTERISTICS
VP = 5 V; TA = +25C, -40C, +85C; CLPA/B = OPEN. Colors: +25C black, -40C blue, +85C red.
5 2.5 2.0 4 A 1.0 1.5
4 OUTN OUTP 1.0 5 2.5 2.0 1.5
OUT[A, B] (V)
OUT [P, N] (V)
ERROR (dB)
3
0.5 0
3
0.5 0
2
B
-0.5 -1.0
2
-0.5 -1.0
1
-1.5 -2.0
05334-060
1
-1.5 -2.0 -50 -40 -30 -20 -10 0 10
05334-065
05334-079
0 -60
-50
-40
-30
-20
-10
0
10
-2.5 20
0 -60
-2.5 20
INPUT AMPLITUDE (dBm)
INPUT AMPLITUDE (dBm)
Figure 3. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at 450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T
5 2.5 2.0 4 1.5 1.0
Figure 6. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 450 MHz, with B Input Held at -25 dBm and A Input Swept, Typical Device, ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T (Note that the OUTP and OUTN Error Curves Overlap)
5 4 3 2 OUTP-OUTN (V) 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -50 -40 -30 -20 -10 0 10 -2.5 20 ERROR (dB)
OUT[A, B] (V)
3
0.5 0
ERROR (dB)
1 0 -1 -2 -3 -4
2
-0.5 -1.0
1
-1.5 -2.0
05334-075
0 -60
-50
-40
-30
-20
-10
0
10
-2.5 20
-5 -60
INPUT AMPLITUDE (dBm)
INPUT AMPLITUDE (dBm)
Figure 4. Distribution of OUT[A, B] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 30 Devices from Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T
0.20 0.15 0.10
Figure 7. Distribution of [OUTP - OUTN] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 30 Devices from Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Differential Drive, PIN Ch. B = -25 dBm, Channel A Swept
4 2 0 +10DEG +2DB +1DB +15DEG
OUTA-OUTB (V)
0.05
ERROR (dB)
-2 REF -4 -6 -8 -15DEG -10DEG
SERIES NAME INDICATES THE POLARITY AND MAGNITUDE OF THE DEVIATION APPLIED TO THE INHA INPUT, RELATIVE TO THE INLA INPUT, AS REFERENCED TO THE REF SIGNAL.
0 -0.05 -0.10
05334-070
-1DB
-0.15 -0.20 -60
-2DB 0 5 10
05334-003
-50
-40
-30
-20
-10
0
10
20
-10 -40
-35
-30
INPUT AMPLITUDE (dBm)
-25 -20 -15 -10 -5 RF INPUT AT INLA (dBm)
Figure 5. Distribution of [OUTA - OUTB] Voltage vs. Input Amplitude over Temperature for at Least 30 Devices from Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T
Figure 8. Log Conformance vs. Input Amplitude at various Amplitude and Phase Balance points, 450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave, Differential Drive
Rev. 0 | Page 9 of 48
ERROR (dB)
AD8364
5 2.5 2.0 4 B A 1.5 1.0
5
2.5 2.0
4
OUTN
OUTP
1.5 1.0
OUT[A, B] (V)
OUT[P, N] (V)
ERROR (dB)
3
0.5 0
3
0.5 0
2
-0.5 -1.0
2
-0.5 -1.0
1
-1.5 -2.0 -50 -40 -30 -20 -10 0 10
05334-061
1
-1.5 -2.0 -50 -40 -30 -20 -10 0 10
05334-066
0 -60
-2.5 20
0 -60
-2.5 20
INPUT AMPLITUDE (dBm)
INPUT AMPLITUDE (dBm)
Figure 9. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at 880 MHz, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun = Mini-Circuits JTX-4-10T
Figure 12. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 880 MHz, with B Input Held at -25 dBm and A Input Swept, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun = JTX-4-10T (Note that the OUTP and OUTN Error Curves Overlap)
5 4 3 2
OUTP-OUTN (V)
5
2.5 2.0
2.5 2.0 1.5 1.0
ERROR (dB)
05334-004
05334-084
4
B A
1.5 1.0
OUT[A, B] (V)
ERROR (dB)
3
0.5 0
1 0 -1 -2 -3 -4
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -50 -40 -30 -20 -10 0 10 20 INPUT AMPLITUDE (dBm)
2
-0.5 -1.0
1
-1.5 -2.0
05334-076
0 -60
-50
-40
-30
-20
-10
0
10
-2.5 20
-5 -60
INPUT AMPLITUDE (dBm)
Figure 10. Distribution of OUT[A, B] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 15 Devices from Multiple Lots, Frequency = 880 MHz, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun =JTX-4-10T
0.20 0.15 0.10
Figure 13. Distribution of [OUTP - OUTN] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 15 Devices from Multiple Lots, Frequency = 880 MHz, ADJ[A, B] =0.5 V, Sine Wave, Differential Drive, PIN Ch. B = -25 dBm, Channel A Swept
4 2 0 -2 -4
ERROR (dB)
+30DEG
+20DEG
-15DEG REF +1dB +10DEG
OUTA-OUTB (V)
0.05 0 -0.05 -0.10
05334-071
-6 -8 -10 -12 -14
+2dB
SERIES NAME INDICATES THE POLARITY
-0.15 -0.20 -60
-16 AND MAGNITUDE OF THE DEVIATION -18
APPLIED TO THE INHA INPUT, RELATIVE TO THE INLA INPUT, AS REFERENCED TO THE REF SIGNAL.
-2dB -1dB -10DEG 0 5 10
-50
-40
-30
-20
-10
0
10
20
-20 -40
-35
-30
INPUT AMPLITUDE (dBm)
-25 -20 -15 -10 -5 RF INPUT AT INLA (dBm)
Figure 11. Distribution of [OUTA - OUTB] Voltage vs. Input Amplitude over Temperature for at Least 15 Devices from Multiple Lots, Frequency = 880 MHz, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun =JTX-4-10T
Figure 14. Log Conformance vs. Input Amplitude at Various Amplitude and Phase Balance points, 880 MHz, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive
Rev. 0 | Page 10 of 48
ERROR (dB)
AD8364
5 2.5 2.0 4 A
OUT[A, B] (V)
5
2.5 2.0
1.5 1.0
OUT[P, N] (V) ERROR (dB)
4 OUTN OUTP
1.5 1.0
3
0.5 0
3
0.5 0
2
-0.5 -1.0
2
-0.5 -1.0
1
B
-1.5 -2.0
05334-062
1
-1.5 -2.0 -50 -40 -30 -20 -10 0 10
05334-067
05334-080
0 -60
-50
-40
-30
-20
-10
0
10
-2.5 20
0 -60
-2.5 20
INPUT AMPLITUDE (dBm)
INPUT AMPLITUDE (dBm)
Figure 15. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at 1.88 GHz, Typical Device, TADJ[A, B]= 0.65 V, Sine Wave, Differential Drive, Balun = Murata LDB181G8820C-110
5 2.5 2.0 4 1.5 1.0
Figure 18. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 1.88 GHz, with B Input Held at -25 dBm and A Input Swept, Typical Device, ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive, Balun = Murata LDB181G8820C-110 (Note that the OUTP and OUTN Error Curves Overlap)
5 4 3 2 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 20
OUTP-OUTN (V)
OUT[A ,B] (V)
ERROR (dB)
3
0.5 0
1 0 -1 -2 -3 -4
2
-0.5 -1.0
1
-1.5 -2.0
05334-083
0 -60
-2.5 -50 -40 -30 -20 -10 0 10 20 INPUT AMPLITUDE (dBm)
-5 -60
-50
-40
-30
-20
-10
0
10
INPUT AMPLITUDE (dBm)
Figure 16. Distribution of OUT[A, B] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 20 Devices from Multiple Lots, Frequency = 1.88 GHz, ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive, Balun = Murata LDB181G8820C-110
0.20 0.15 0.10
OUTA-OUTB (V)
Figure 19. Distribution of [OUTP - OUTN] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 20 Devices from Multiple Lots, Frequency = 1.88 GHz, ADJ[A, B] =0.65 V, Sine Wave, Differential Drive, PIN Ch. B = -25 dBm, Channel A Swept
2 0 -2 -4 REF -1dB +10deg +30deg +2dB -2dB +20DEG
0.05
ERROR (dB)
-6 -8 -10 -12
-10deg -30deg -20deg +1dB
0 -0.05 -0.10
-14 SERIES NAME INDICATES THE POLARITY
05334-072
-0.15 -0.20 -60
AND MAGNITUDE OF THE DEVIATION
-16 APPLIED TO THE INHA INPUT, RELATIVE -18 -40
TO THE INLA INPUT, AS REFERENCED TO THE REF SIGNAL.
-50
-40
-30
-20
-10
0
10
20
-35
-30
INPUT AMPLITUDE (dBm)
-25 -20 -15 -10 -5 RF INPUT AT INLA (dBm)
0
5
10
Figure 17. Distribution of [OUTA - OUTB] Voltage vs. Input Amplitude over Temperature for at Least 20 Devices from Multiple Lots, Frequency = 1.88 GHz, ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive, Balun = Murata LDB181G8820C-110
Figure 20. Log Conformance vs. Input Amplitude at Various Amplitude and Phase Balance Points, 1.880 GHz, Typical Device, ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive
Rev. 0 | Page 11 of 48
05334-005
ERROR (dB)
ERROR (dB)
AD8364
5 2.5 2.0 4
B
5
2.5 2.0
1.5 1.0
4 OUTN OUTP
1.5 1.0
OUT[A, B] (V)
OUT[P, N] (V)
ERROR (dB)
3
0.5 0
3
0.5 0
2
-0.5 -1.0
A
2
-0.5 -1.0
1
-1.5 -2.0
05334-063
1
-1.5 -2.0 -50 -40 -30 -20 -10 0 10
05334-068
0 -60
-50
-40
-30
-20
-10
0
10
-2.5 20
0 -60
-2.5 20
INPUT AMPLITUDE (dBm)
INPUT AMPLITUDE (dBm)
Figure 21. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at 2.14 GHz, Typical Device, ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata LDB212G1020C-001
Figure 24. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 2.14 GHz, with B Input Held at -25 dBm and A Input Swept, Typical Device, ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata LDB212G1020C-001 (Note that the OUTP and OUTN Error Curves Overlap)
5 4 3 2 OUTP-OUTN (V) 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -50 -40 -30 -20 -10 0 10
05334-081
05334-006
5
2.5 2.0
4
B
1.5 1.0
OUT[A, B] (V)
ERROR (dB)
3
0.5 0
1 0 -1 -2 -3 -4
2
-0.5 -1.0
A
1
-1.5 -2.0
05334-077
0 -60
-50
-40
-30
-20
-10
0
10
-2.5 20
-5 -60
-2.5 20
INPUT AMPLITUDE (dBm)
INPUT AMPLITUDE (dBm)
Figure 22. Distribution of OUT[A, B] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 3 Devices from Multiple Lots, Frequency = 2.14 GHz, ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata LDB212G1020C-001
0.20 0.15 0.10 OUTA-OUTB (V) 0.05
Figure 25. Distribution of [OUTP - OUTN] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 3 Devices from Multiple Lots, Frequency = 2.14 GHz, ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, PIN Ch. B = -25 dBm, Channel A Swept
4 2 0 -2 -4 -6 +2dB -1dB REF +1dB -10DEG +20DEG +10DEG +30DEG
-2dB
ERROR (dB)
-8 -10 -12 -14 -16
0 -0.05 -0.10
05334-073
-18 SERIES NAME INDICATES THE POLARITY -20 APPLIED TO THE INHA INPUT, RELATIVE -22 TO THE INLA INPUT, AS REFERENCED TO
THE REF SIGNAL. AND MAGNITUDE OF THE DEVIATION
-0.15 -0.20 -60
-20DEG -30DEG 0 5 10
-50
-40
-30
-20
-10
0
10
20
-24 -40
-35
-30
INPUT AMPLITUDE (dBm)
-25 -20 -15 -10 -5 RF INPUT AT INLA (dBm)
Figure 23. Distribution of [OUTA - OUTB] Voltage vs. Input Amplitude over Temperature for 3 Devices from Multiple Lots, Frequency = 2.14 GHz, ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata LDB212G1020C-001
Figure 26. Log Conformance vs. Input Amplitude at Various Amplitude and Phase Balance Points, 2.140 GHz, Typical Device, ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive
Rev. 0 | Page 12 of 48
ERROR (dB)
ERROR (dB)
AD8364
5
5 2.5 2.0 4 1.5
2.5 2.0
4 OUTN OUTP
1.5 1.0 0.5 0
OUT[P, N] (V)
3
OUT[A, B] (V)
3
A
0.5 0 -0.5 -1.0
B
ERROR (dB)
2
-0.5 -1.0
2
1
-1.5 -2.0 -50 -40 -30 -20 -10 0 10
05334-069
05334-082
1
-1.5 -2.0 -50 -40 -30 -20 -10 0 10
05334-064
0 -60
-2.5 20
0 -60
-2.5 20
INPUT AMPLITUDE (dBm)
INPUT AMPLITUDE (dBm)
Figure 27. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at 2.5 GHz, Typical Device, ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata LDB182G4520C-110
5 2.5 2.0 4 1.5 1.0
Figure 30. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 2.5 GHz, with B Input Held at -25 dBm and A Input Swept, Typical Device, ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata LDB182G4520C-110 (Note that the OUTP and OUTN Error Curves Overlap)
5 4 3 2 OUTP-OUTN (V) 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -50 -40 -30 -20 -10 0 10 -2.5 20 ERROR (dB)
05334-007
OUT[A, B] (V)
3
0.5 0
ERROR (dB)
1 0 -1 -2 -3 -4
2
-0.5 -1.0
1
-1.5 -2.0 -50 -40 -30 -20 -10 0 10
05334-078
0 -60
-2.5 20
-5 -60
INPUT AMPLITUDE (dBm)
INPUT AMPLITUDE (dBm)
Figure 28. Distribution of OUT[A, B] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 15 Devices from Multiple Lots, Frequency = 2.5 GHz, ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata LDB182G4520C-110
0.20 0.15 0.10
Figure 31. Distribution of [OUTP - OUTN] Voltage and Error over Temperature After Ambient Normalization vs. Input Amplitude for at Least 15 Devices from Multiple Lots, Frequency = 2.5 GHz, ADJ[A, B] =1.1 V, Sine Wave, Differential Drive, PIN Ch. B = -25 dBm, Channel A Swept
4 2 0 -2 -4 -6 +20DEG REF +30DEG -10DEG +1dB +10DEG +2dB -20DEG -30DEG
MAGNITUDE OF THE DEVIATION APPLIED TO AS REFERENCED TO THE REF SIGNAL.
-2dB -1dB
OUTA-OUTB (V)
0.05
ERROR (dB)
-8 -10 -12 -14 -16 -18
0 -0.05 -0.10
05334-074
-0.15 -0.20 -60
-20 SERIES NAME INDICATES THE POLARITY AND -22 THE INHA INPUT, RELATIVE TO THE INLA INPUT, -24 -40 -35 -30 -25 -20 -15 -10 -5 RF INPUT AT INLA (dBm) 0 5 10
-50
-40
-30
-20
-10
0
10
20
INPUT AMPLITUDE (dBm)
Figure 29. Distribution of [OUTA - OUTB] Voltage vs. Input Amplitude over Temperature for at Least 15 Devices from Multiple Lots, Frequency = 2.5 GHz, ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata LDB182G4520C-110
Figure 32. Log Conformance vs. Input Amplitude at Various Amplitude and Phase Balance Points, 2.500 GHz, Typical Device, ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive
Rev. 0 | Page 13 of 48
ERROR (dB)
1.0
AD8364
2.0 1.5 ERROR CW 1.0 ERROR 256 QAM 8dB CF 0.5 0.5 ERROR QPSK 4dB CF 1.0 2.0 1.5
ERROR (dB)
0 -0.5 -1.0 -1.5 ERROR 16C CDMA2K 9CH SR1 14dB CF ERROR 1C TM1-32 DPCH 13dB CF
05334-008
ERROR (dB)
0 ERROR CW -0.5 -1.0 -1.5 ERROR 3 CARRIER CDMA2K SR1 ERROR 4 CARRIER WCDMA TM 1-64 0 5 10 15 20
05334-010 05334-011
-2.0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN MEAS (dBm)
0
5
10 15 20
-2.0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN MEAS (dBm)
Figure 33. Output Error from CW Linear Reference vs. Input Amplitude with Different Waveforms, CW, QPSK, 256QAM, WCDMA 1-Carrier Test Model 1 with 32 DPCH, CDMA2000, 16-Carrier, 9-Channel SR1 Frequency 2.140 GHz, CLP[A, B] = 1 F, Balun = Murata LDB212G1020C-001
2 1.5 1.0 ERROR 2 CARRIER TM1-64 ERROR CW
Figure 35. Output Voltage and Error from CW Linear Reference vs. Input Amplitude with Different Waveforms, CW, 3-Carrier CDMA2000 SR1, 4-Carrier WCDMA, Test Model 1 with 64 DPCH, Frequency 2.140 GHz, Balun = Murata LDB212G1020C-001
2.0 1.5 1.0
ERROR FWD 1 CARRIER CDMA2K PILOTSR1
ERROR CW ERROR FWD 4 CARRIER CDMA2K 9CH SR1 ERROR FWD 1 CARRIER CDMA2K 9CH SR1
ERROR (dB)
ERROR (dB)
0.5 0 -0.5 -1.0 -1.5
ERROR 4 CARRIER TM1-64
0.5 0 -0.5 -1.0
ERROR 3 CARRIER TM1-64 ERROR 1 CARRIER TM1-64
05334-009
-1.5
ERROR FWD 4 CARRIER CDMA2K 9CH SR1
ERROR FWD 16 CARRIER CDMA2K 9CH SR1
-2.0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN MEAS (dBm)
0
5
10 15 20
-2.0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN MEAS (dBm)
ERROR FWD 3 CARRIER CDMA2K 9CH SR1
0
5
10 15 20
Figure 34. Error from CW Linear Reference vs. Input Amplitude with Different Waveforms, CW, WCDMA1, 2-, 3-, and 4-Carrier, Test Model 1 with 64 DPCH, Frequency 2.14 GHz, Balun = Murata LDB212G1020C-001
Figure 36. Error from CW Linear Reference vs. Input Amplitude with Different Waveforms, CW, 1-Carrier CDMA2000 Pilot CH SR1, 1-Carrier CDMA2000 9CH SR1, 3-Carrier CDMA2000 9CH SR1, 4-Carrier CDMA2000 9CH SR1 Frequency 16-Carrier CDMA2000 9CH SR1, Frequency 2.140 GHz, Balun = Murata LDB212G1020C-001
Rev. 0 | Page 14 of 48
AD8364
90 120 60
20
150
30
15 10
180
0
CHANGE IN VREF (mV)
05334-053
5 0 -5 -10 -15
05334-014 05334-057
210
330
240
300 270
-20 -40 -30 -20 -10
0
10 20 30 40 50 TEMPERATURE (C)
60
70
80
90
Figure 37. Differential Input Impedance (S11) vs. Frequency; ZO = 50
14 12 10 TOTAL = 40 DEVICES RF INPUT = -60dBm
Figure 40. Change in VREF vs. Temperature for 11 Devices
10000
450MHz, -40dB 450MHz, 0dB 450MHz, -20dB
OUTPUT NOISE (nV/ Hz)
8
1000
2140MHz, -20dB 2140MHz, 0dB 2140MHz, -40dB
COUNT
6 4 2
100
450MHz, RF OFF
0 2.486 2.488 2.490 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 VREF (V)
05334-012
10 100
450MHz 1k 10k 100k FREQUENCY (Hz) 1M 10M
Figure 38. Distribution of VREF for 40 Devices
14 12 TOTAL = 40 DEVICES RF INPUT = -60dBm
Figure 41. Noise Spectral Density of OUT[A, B]; CLP[A, B] = Open
10000 0dB
10
OUTPUT NOISE (nV/ Hz)
8
1000 -20dB -40dB
COUNT
6 4 2 0 0.617 0.619 0.621 0.623 VREF (V) 0.625 0.627
100
RF OFF
05334-013
05334-059
10 100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 39. Distribution of TEMP Voltage for 40 Devices
Figure 42. Noise Spectral Density of OUT[P, N]; CLP[A, B] = 0.1 F, Frequency = 2140 MHz
Rev. 0 | Page 15 of 48
AD8364
10000
PWDN
0dB OUTPUT NOISE (nV/ Hz) 1000 -20dB
2
OUTA CARRIER FREQUENCY 450MHz, CLPA = OPEN 0dBm
-40dB
100
-20dBm -40dBm
VDD = 5V VA = 5V VB = 0V
B2
1k
10k
100k
1M
10M
05334-058
10 100
FREQUENCY (Hz)
REF2 1.0V 4.0s
Figure 43. Noise Spectral Density of OUT[A, B]; CLP[A, B] = 0.1 F, Frequency = 2140 MHz
Figure 46. Output Response Using Power-Down Mode for Various RF Input Levels, Carrier Frequency 450 MHz, CLPA = Open
PWDN
RF BURST ENABLE
2 2
OUTA CARRIER FREQUENCY 450MHz, CLPA = OPEN
OUTA CARRIER FREQUENCY 450MHz, CLPA = 0.1F 0dBm
0dBm -20dBm -40dBm VDD = 5V VA = 5V VB = 0V
-20dBm -40dBm VDD = 5V VA = 5V VB = 0V
B2
05334-015
B2
05334-018
CH2 5.0V CH4 1.0V REF2 1.0V 2.0s
M2.0s 1.25GS/s A CH2 2.1V
800ps/pt
CH2 5.0V CH4 1.0V REF2 1.0V 2.0s
M2.0ms 1.25MS/s A CH2 1.7V
800ns/pt
Figure 44. Output Response to RF Burst Input for Various RF Input Levels, Carrier Frequency 450 MHz, CLPA = Open
Figure 47. Output Response Using Power-Down Mode for Various RF Input Levels, Carrier Frequency 450 MHz, CLPA = 0.1 F, CHPA = 10 nF
RF BURST ENABLE
2
OUTA CARRIER FREQUENCY 450MHz, CLPA = 0.1F 0dBm VDD = 5V VA = 5V VB = 0V
-20dBm -40dBm
B2
05334-016
CH2 5.0V CH4 1.0V REF2 1.0V 2.0ms
M2.0s 1.25MS/s A CH2 2.1V
800ns/pt
Figure 45. Output Response to RF Burst Input for Various RF Input Levels, Carrier Frequency 450 MHz, CLPA = 0.1 F
Rev. 0 | Page 16 of 48
05334-017
RF OFF
CH2 5.0V CH4 1.0V
M4.0s 625MS/s A CH2 2.1V
1.6ns/pt
AD8364
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5
05334-019
80 70 60 50 40 30 20 10
05334-020
SUPPLY CURRENT (mA)
ERROR (dB)
VPWDN INCREASING VPWDN DECREASING
-2.0 -60
-50
-40
-30 -20 -10 RF INPUT (dBm)
0
10
20
0 1.0
1.2
1.4
1.6 1.8 VPWDN (V)
2.0
2.2
2.4
Figure 48. Output Voltage Stability vs. VP (Supply Voltage) at 2.14 GHz, When VP Varies by 10%,ADJ[A, B] =0.85 V, Sine Wave, Differential Drive, Murata LDB212G1020C-001
Figure 49. Supply Current vs. VPWDN
Rev. 0 | Page 17 of 48
AD8364 GENERAL DESCRIPTION AND THEORY
ACOM ACOM
18
COMA
DECA
CHPA
TEMP
VPSR
The AD8364 is a dual-channel, 2.7 GHz, true rms responding detector with 60 dB measurement range. It incorporates two AD8362 channels with shared reference circuitry (See the AD8362 datasheet for more information). Multiple enhancements have been made to the AD8362 cores to improve measurement accuracy. Log-conformance peak-to-peak ripple has been reduced to <0.2 dB over the entire dynamic range. Temperature stability of the rms output measurements provides <0.5 dB error over the specified temperature range of -40C to 85C through proprietary techniques. The use of well-matched channels offers extremely temperature-stable difference outputs, OUTP and OUTN. Given well-matched channels through IC integration, the rms measurement outputs, OUTA and OUTB, drift in the same manner. With OUTP shorted to FBKA, the function at OUTP is OUTP = OUTA - OUTB + VLVL (1)
24
23
22
21
20
19
17
TEMP VPSA 25 INHA 26 INLA 27 PWDN 28 COMR 29 INLB 30 INHB 31 VPSB 32 BIAS
1 2 3
VGA CONTROL
ISIG2 ITGT2
CLPA
16 VSTA 15 OUTA 14 FBKA 13 OUTP 12 OUTN 11 FBKB 10 OUTB 9 VSTB
CHANNEL A TruPwrTM
OUTA OUTB
CHANNEL B TruPwrTM
ISIG2 ITGT2
VGA CONTROL
4 5 6 7 8
05334-001
VLVL
DECB
CHPB
When OUTN is shorted to FBKB, the function at OUTN is OUTN = OUTB - OUTA + VLVL (2)
VIN INH[A, B]
Figure 50. Block Diagram
OUTP and OUTN are insensitive to the common drift due to the difference cancellation of OUTA and OUTB. The AD8364 is a fully calibrated rms-to-dc converter capable of operating on signals of a few hertz to 2.7 GHz or more. Unlike logarithmic amplifiers, the AD8364 response is waveform independent. The device accurately measures waveforms that have a high peak-to-rms ratio (crest factor). Figure 50 shows a block diagram. A single channel of the AD8364 consists of a high performance AGC loop. As shown in Figure 51, the AGC loop comprises a wide bandwidth variable gain amplifier (VGA), square law detectors, an amplitude target circuit, and an output driver. For a more detailed description of the functional blocks, see the AD8362 data sheet.
COMB
VGA INL[A, B] CHP[A, B] OFFSET NULLING VST[A, B] VST[A, B] VSIG GSET
x2
x2
TEMPERATURE COMPENSATION
CLPB
ADJB
ADJA
VREF
ADJ[A, B]
VREF x 0.03 OUTPUT BUFFER CF OUT[A, B]
SETPOINT INTERFACE CLP [A, B]
VREF VREF 2.5V
BAND GAP REFERENCE
ACOM
Figure 51. Single-Channel Details
Rev. 0 | Page 18 of 48
05334-023
CLPF EXTERNAL
AD8364
SQUARE LAW DETECTOR AND AMPLITUDE TARGET
The output of the VGA, called VSIG, is applied to a wideband square law detector. The detector provides the true rms response of the RF input signal, independent of waveform, up to a crest factor of 6. The detector output, called ISQU, is a fluctuating current with positive mean value. The difference between ISQU and an internally generated current, ITGT[A, B], is integrated by CF and a capacitor attached to CLP[A, B]. CF is the on-chip 25 pF filter capacitor. CLP[A, B] can be used to arbitrarily increase the averaging time while trading off response time. When the AGC loop is at equilibrium, MEAN(ISQU) = ITGT[A, B] This equilibrium occurs only when MEAN(VSIG2) = VTGT[A, B]2 where VTGT is an attenuated version of the VREF voltage. Because the square law detectors are electrically identical and well matched, process and temperature dependant variations are effectively cancelled. By forcing the above identity through varying the VGA setpoint, it is apparent that RMS(VSIG) = (MEAN(VSIG2)) = (VTGT2) = VTGT Substituting the value of VSIG, we have RMS(G0 x RFIN exp(-VST[A, B]/VGNS)) = VTGT When connected as a measurement device VST[A, B] = OUT[A, B]. Solving for OUT[A, B] as a function of RFIN, OUT[A, B] = VSLOPE x Log10(RMS(RFIN)/VZ) (7) (6)
05334-024
RF INPUT INTERFACE
The AD8364's RF inputs are connected as shown in Figure 52. There are 100 resistors connected between DEC[A, B] and INH[A, B] and also between DEC[A, B] and INL[A, B]. The DEC[A, B] pins have a dc level established as (7 x VPS[A, B] + 55 x VBE)/30. With a 5 V supply, DEC[A, B] is approximately 2.5 V. Signal-coupling capacitors must be connected from the input signal to the INH[A, B] and INL[A, B] pins. The high-pass corner is fhigh-pass = 1/(2 x x 100 x C) (8)
(3)
(4)
A decoupling capacitor should be connected from DEC[A, B] to ground to attenuate any signal at the midpoint. A 100 pF and 0.1 F cap from DEC[A, B] to ground are recommended, with a 1 nF coupling capacitor such that signals greater than 1.6 MHz can be measured. For coupling signals less than 1.6 MHz, 100 x Ccoupling for the DEC[A, B] capacitor generally can be used.
DEC[A, B] COM[A, B] INH[A, B] 100 VSP[A, B]
(5)
INL[A, B]
VIN 100
VGA
VSP[A, B]
VSP[A, B]
COM[A, B] COM[A, B]
Figure 52. AD8364 RF Inputs
where VSLOPE is laser trimmed to 1 V/decade (or 50 mV/dB) at 100 MHz. VZ is the intercept voltage, since Log 10(1) = 0 when RMS(RFIN) = VZ. If desired, the effective value of VSLOPE may be altered by using a resistor divider from OUT[A, B] to drive VST[A, B]. The intercept, VZ, is also laser trimmed to 180 V (-62 dBm, referred to 50 ) with a CW signal at 100 MHz. This value is extrapolated, because OUT[A, B] do not respond to input of less than approximately -55 dBm with differential drive. In most applications, the AGC loop is closed through the setpoint interface, VST[A, B]. In measurement mode, OUT[A, B] are tied to VST[A, B], respectively. In controller mode, a control voltage is applied to VST[A, B]. Pins OUT[A, B] drive the control input of a system. The RF feedback signal to the input pins is forced to have an rms value determined by VSTA or VSTB.
OFFSET COMPENSATION
An offset-nulling loop is used to address small dc offsets in the VGA. The high-pass corner frequency of this loop is internally preset to about 1 MHz using an on-chip capacitor of 25 pF (1/(2 x 5K x 25 pF)), which is sufficiently low for most HF applications. The high-pass corner can be reduced by a capacitor from CHP[A, B] to ground. The input offset voltage varies depending on the actual gain at which the VGA is operating and, thus, on the input signal amplitude. When an excessively large value of CHP[A, B] is used, the offset correction process may lag the more rapid changes in the VGA's gain, which may increase the time required for the loop to fully settle for a given steady input amplitude.
Rev. 0 | Page 19 of 48
AD8364
TEMPERATURE SENSOR INTERFACE
The AD8364 provides a temperature sensor output capable of driving about 1.6 mA. A 330 -equivalent internal resistance is connected from TEMP to COMR to provide current sink capability. The temperature scaling factor of the output voltage is approximately 2 mV/C. The typical absolute voltage at 25C is about 620 mV.
VPSR INTERNAL VPTAT TEMP 4k 350 1k
05334-025
POWER-DOWN INTERFACE
The operating and stand-by currents for the AD8364 at 25C are approximately 70 mA and 500 A, respectively. The PWDN pin is connected to an internal resistor divider made with two 42 k resistors. The divider voltage is applied to the base of an NPN transistor to force a power-down condition when the device is active. Typically when PWDN is pulled greater than 2 V, the device is powered down. Figure 46 and Figure 47 show typical response times for various RF input levels. The output reaches to within 0.1 dB of its steady-state value in about 1.6 s; the reference voltage is available to full accuracy in a much shorter time. This wake-up response vary depending on the input coupling means and the capacitances CDEC[A, B], CHP[A, B], and CLP[A, B].
PWDN 42k POWER DOWN SIGNAL
COMR
Figure 53. TEMP Interface Simplified Schematic
42k
05334-027
VREF INTERFACE
An internal voltage reference is provided to the user at Pin VREF. The VREF voltage is a temperature stable 2.5 V reference that can drive about 18 mA. An 830 equivalent internal resistance is connected from VREF to ACOM for 3 mA sink capability.
VPSR INTERNAL VOLTAGE VREF 9k 900 1.465k
05334-026
COMR
Figure 55. PWDN Interface Simplified Schematic
VST[A, B] INTERFACE
The VST[A, B] interface has a high input impedance of 72 k. The voltage at VST[A, B] is converted to an internal current used to steer the VGA gain. The VGA attenuation control is set to 20 dB/V.
GAIN ADJUST 1.35A/dB VST[A, B] 36k
COMR
36k 18.5k
05334-028
Figure 54. VREF Interface Simplified Schematic
ACOM
Figure 56. VST[A, B] Interface Simplified Schematic
Rev. 0 | Page 20 of 48
AD8364
OUT[A, B, P, N] OUTPUTS
The output drivers used in the AD8364 are different than the output stage on the AD8362. The AD8364 incorporates rail-torail output drivers with pull-up and pull-down capabilities. The output noise is approximately 40 nV/Hz at 100 kHz. OUT[A, B, P, N] can source and sink up to 70 mA. There is also an internal load from both OUTA and OUTB to ACOM of 2.5 k.
1k OUTA OUTB 1k 1k FBKA VLVL 1k
VPS[A, B]
VLVL 1k
VPSR
OUTP
COMR VPSR
1k OUTN
05334-030
OUTB OUTA 1k 1k
OUT[A, B] 2k
INTERNAL VOLTAGE
FBKB
COMR
Figure 58. OUT[P, N] Interface Simplified Schematic
COM[A, B] 500
05334-029
ACOM
Figure 57. OUT[A, B] Interface Simplified Schematic
Rev. 0 | Page 21 of 48
AD8364
MEASUREMENT CHANNEL DIFFERENCE OUTPUT USING OUT[P, N]
The AD8364 incorporates two operational amplifiers with railto-rail output capability to provide a channel difference output. As in the case of the output drivers for OUT[A, B], the output stages have the capability of driving 70 mA. The output noise is approximately 40 nV/Hz at 100 kHz. OUTA and OUTB are internally connected through 1 k resistors to the inputs of each op amp. The pin VLVL is connected to the positive terminal of both op amps through 1 k resistors to provide level shifting. The negative feedback terminal is also made available through a 1 k resistor. The input impedance of VLVL is 1 k and FBK[A, B] is 2 k. See Figure 59 for the connections of these pins.
ACOM ACOM COMA DECA CHPA TEMP VPSR CLPA
CONTROLLER MODE
The channel difference outputs can be used for controlling a feedback loop to the AD8364's RF inputs. A capacitor connected between FBKA and OUTP forms an integrator, keeping in mind that the on-chip 1 k feedback resistor forms a zero. (The value of the on-chip resistors can vary as much as 20% with manufacturing process variation.) If Channel A is driven and Channel B has a feedback loop from OUTP through a PA, then OUTP integrates to a voltage value such that OUTB = (OUTA + VLVL)/2 (11)
The output value from OUTN may or may not be useful. It is given by OUTN = 0 V For VLVL < OUTA/3, (12)
24
23
22
21
20
19
18
17
TEMP VPSA 25 INHA 26 INLA 27 PWDN 28 COMR 29 INLB 30 INHB 31 VPSB 32 BIAS
1 2 3
VGA CONTROL
ISIG2 ITGT2
16 15 14 13 12 11 10 9
VSTA OUTA FBKA OUTP OUTN FBKB OUTB VSTB
Otherwise, OUTN = (3 x VLVL - OUTA)/2 (13)
CHANNEL A TruPwrTM
OUTA OUTB
CHANNEL B TruPwrTM
ISIG2 ITGT2
VGA CONTROL
4 5 6 7 8
05334-001
Figure 59. Op Amp Connections (All Resistors are 1 k 20%)
If VLVL is connected to OUTA, then OUTB is forced to equal OUTA through the feedback loop. This flexibility provides the user with the capability to measure one channel operating at a given power level and frequency while forcing the other channel to a desired power level at another frequency. ADJA and ADJB should be set to different voltage levels to reduce the temperature drift of the output measurement. The temperature drift will be statistical sum of the drift from Channel A and Channel B. As stated before, VLVL can be used to force the slaved channel to operate at a different power than the other channel. If the two channels are forced to operate at different power levels, then some static offset occurs due to voltage drops across metal wiring in the IC. If an inversion is necessary in the feedback loop, OUTN can be used as the integrator by placing a capacitor between OUTN and OUTP. This changes the output equation for OUTB and OUTP to OUTB = 2 x OUTA - VLVL For VLVL < OUTA/2, OUTN = 0 V Otherwise, OUTN = 2 x VLVL - OUTA (16) (15) (14)
VLVL
DECB
CHPB
If OUTP is connected to FBKA, then OUTP is given as OUTP = OUTA - OUTB + VLVL If OUTN is connected to FBKB, then OUTN is given as OUTN = OUTB - OUTA + VLVL (10) (9)
In this configuration, all four measurements, OUT[A, B, P, N], are made available simultaneously. A differential output can be taken from OUTP - OUTN, and VLVL can be used to adjust the common-mode level for an ADC connection.
COMB
CLPB
ADJB
ADJA
VREF
The previous equations are valid when Channel A is driven and Channel B is slaved through a feedback loop. When Channel B is driven and Channel A is slaved, the above equations can be altered by changing OUTB to OUTA and OUTN to OUTP.
Rev. 0 | Page 22 of 48
AD8364
RF MEASUREMENT MODE BASIC CONNECTIONS
The AD8364 requires a single supply of nominally 5 V. The supply is connected to the three supply pins, VPSA, VPSB, and VPSR. Each pin should be decoupled using the two capacitors with values equal or similar to those shown in Figure 60. These capacitors must provide a low impedance over the full frequency range of the input, and they should be placed as close as possible to the VPOS pins. Two different capacitors are used in parallel to provide a broadband ac short to ground. The input signals are applied to the input differentially. The RF inputs of the AD8364 have a differential input impedance of 200 . When the AD8364 RF inputs are driven from a 50 source, a 4:1 balun transformer is recommended to provide the necessary impedance transformation. The inputs can be driven single-ended, however, this reduces the measurement range of the rms detectors (see the Single-Ended Input Operation section). Table 4. Baluns Used to Characterize the AD8364
Frequency 450 MHz 880 MHz 1880 MHz 2140 MHz 2500 MHz Balun MIA-COM ETK4-2T Mini-Circuits JTX-4-10T Murata LDB181G8820C-110 Murata LDB212G1020C-001 Murata LDB182G4520C-110
The device is placed in measurement mode by connecting OUTA and/or OUTB to VSTA and/or VSTB, respectively. This closes the AGC loop within the device with OUT[A, B] representing the VGA control voltage, which is required to present the correct rms voltage at the input of the internal square law detector. As the input signal to Channel A and Channel B are swept over their nominal input dynamic range of +10 dBm to -50 dBm, the output swings from 0 V to 3.5 V. The voltages OUTA and OUTB are also internally applied to a difference amplifier with a gain of two. So as the dB difference between INA and INB ranges from approximately -30 dB to +30 dB, the difference voltage on OUTP and OUTN swings from -3.5 V to +3.5 V. Input differences larger than 30 dB can be measured as long as the absolute input level at INA and INB are within their nominal ranges of +10 dBm to -50 dBm. However, measurement of large differences between INA and INB are affected by on-chip signal leakage (see the Channel Isolation section). The common-mode level of OUTP and OUTN is set by the voltage applied to VLVL. These output can be easily biased up to a common-mode voltage of 2.5 V by connecting VREF to VLVL. As the gain range is swept, OUTP swings from approximately 1 V to 4.5 V and OUTN swings from 4.5 V to 1 V.
Rev. 0 | Page 23 of 48
AD8364
VPOS R24 0 C23 100pF VPOS R5 0 C8 0.1F C13 0.1F C12 100pF C14 0.1F
24 23 22 21 20 19 18 17
C11 0.1F
C9 0.1F
C10 100pF C5 0.1F INPA
1:4
CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA
25 VPSA
VSTA 16
T2
C7 0.1F
26 INHA
OUTA 15
OUTA
27 INLA
FBKA 14
C6 0.1F
AD8364ACPZ
28 PWDN
OUTP 13 OUTN 12 FBKB 11
OUTP OUTN
T1
1:4
C4 0.1F
29 COMR
30 INLB
INPB C2 0.1F C3 0.1F
31 INHB
EXPOSED PADDLE
OUTB 10 VSTB 9
OUTB
32 VPSB
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
1 C20 100pF C22 0.1F 2 3 4 5 6 7 8
R201 C24 100pF R191
C19 R181 0.1F
C16 0.1F
C21 0.1F
C1 0.1F
1SEE TEXT.
Figure 60. Basic Connections for Operation in Measurement Mode
CONTROLLER MODE BASIC CONNECTIONS
In addition to being a measurement device, the AD8364 can also be configured to measure and control rms signal levels. The AD8364 has two controller modes. Each of the two rms log detectors can be separately configured to set and control the output power level of a variable gain amplifier (VGA) or variable voltage attenuator (VVA). Alternatively, the two rms log detectors can be configured to measure and control the gain of an amplifier or signal chain.
recommended maximum input level for optimum linearity and temperature stability at the frequency of operation. VSTA and OUTA are no longer shorted together. OUTA now provides a bias or gain control voltage to the VGA. The gain control sense of the VGA must be negative and monotonic, that is, increasing voltage tends to decrease gain. However, the gain control transfer function of the device does not need to be well controlled or particularly linear. If the gain control sense of the VGA is positive, an inverting op amp circuit with a dc offset shift can be used between the AD8364 and the VGA to keep the gain control voltage in the 0 V to 5 V range. VSTA becomes the setpoint input to the system. This can be driven by a DAC, as shown in Figure 61, if the output power is expected to vary, or it can simply be driven by a stable reference voltage if constant output power is required. This DAC should have an output swing that covers the 0 V to 3.5 V range. The AD7391 and AD7393 serial-input and parallel-input 10-bit DACs provide adequate resolution (4 mV/bit) and an output swing up to 4.5 V.
Automatic Power Control
Figure 61 shows how the device should be reconfigured to control output power. The RF input to the device is configured as before. A directional coupler taps off some of the power being generated by the VGA (typically a 10 dB to 20 dB coupler is used). A power splitter can be used instead of a directional coupler if there are no concerns about reflected energy from the next stage in the signal chain. Some additional attenuation may be required to set the maximum input signal at the AD8364 to be equal to the
Rev. 0 | Page 24 of 48
05334-031
VPOS
R171
AD8364
When VSTA is set to a particular value, the AD8364 compares this value to the equivalent input power present at the RF input. If these two values do not match, OUTA increases or decreases in an effort to balance the system. The dominant pole of the error amplifier/integrator circuit that drives OUTA is set by the capacitance on Pin CLPA; some experimentation may be necessary to choose the right value for this capacitor. In general, CLPA should be chosen to provide stable loop operation for the complete output power control range. If the slope (in dB/V) of the gain control transfer function of the VGA is not constant, CLPA must be chosen to guarantee a stable loop when the gain control slope is at its maximum. On the other hand, CLPA must provide adequate averaging to the internal low range squaring detector so that the rms computation is valid. Larger values of CLPA tend to make the loop less responsive. The relationship between VSTA and the RF input follows from the measurement mode behavior of the device. For example, from Figure 9, which shows the measurement mode transfer function at 880 MHz, it can be seen that an input power of -10 dBm yields an output voltage of 2.5 V. Therefore, in controller mode, VSTA should be set to 2.5 V, which results in an input power of -10 dBm to the AD8364.
Automatic Gain Control
Figure 62 shows how the AD8364 can be connected to provide automatic gain control to an amplifier or signal chain. Additional pins are omitted for clarity. In this configuration, both rms detectors are connected in measurement mode with appropriate filtering being used on CLP[A, B] to effect a valid rms computation on both channels. OUTA, however, is also connected to the VLVL pin of the on-board difference amplifier. Also, the OUTP output of the difference amplifier drives a variable gain element (either VVA or VGA) and is connected back to the FBKA input via a capacitor so that it is operating as an integrator. Assume that OUTA is much bigger than OUTB. Because OUTA also drives VLVL, this voltage is also present on the noninverting input of the op amp driving OUTP. This results in a net current flow from OUTP through the integrating capacitor into the FBKA input. This results in the voltage on OUTP increasing. If the gain control transfer function of the VVA/VGA is positive, this increases the gain, which in turn increases the input signal to INHB. The output voltage on the integrator continues to increase until the power on the two input channels is equal, resulting in a signal chain gain of unity. If a gain other than 0 dB is required, an attenuator can be used in one of the RF paths, as shown in Figure 62. Alternatively, power splitters or directional couplers of different coupling factors can be used. Another convenient option is to apply a voltage on VLVL other than OUTA. Refer to Equation 11 and the Controller Mode section for more detail. If the VGA/VVA has a negative gain control sense, the OUTN output of the difference amplifier can be used with the integrating capacitor tied back to FBKB. The choice of the integrating capacitor affects the response time of the AGC loop. Small values give a faster response time but can result in instability, whereas larger values reduce the response time. Note that in this mode, the capacitors on CLPA and CLPB, which perform the rms averaging function, must still be used and also affect the loop response time.
PIN
VGA OR VVA (OUTPUT POWER DECREASES AS VAPC INCREASES) VAPC
POUT
ATTENUATOR (0V TO 4.9V AVAILABLE SWING) OUTA INHA C7 0.1F C5 0.1F
1:4
T2
AD8364
INLA VSTA INHA C6 0.1F
DAC
0V TO 3.5V
Figure 61. Operation in Controller Mode for Automatic Power Control
Rev. 0 | Page 25 of 48
05334-032
SEE TEXT
AD8364
DIRECTIONAL OR POWER SPLITTER VGA/VVA DIRECTIONAL OR POWER SPLITTER
CLPF
C5 0.1F
1:4
T1 1:4
C7 0.1F INHA INLA C6 0.1F CHANNEL A TruPwrTM
VGA CONTROL ISIG2 ITGT2
IERR VSTA OUTA FBKA OUTP CINT ATTENUATOR
AD8364
T2 1:4
1:4
OUTA OUTB
DIFF OUT + OUTN FBKB
C4 0.1F INLB INHB CHANNEL B ISIG2 TruPwrTM ITGT2 VGA CONTROL
OUTB
C2 0.1F
C3 0.1F
VSTB
VLVL
CLPF
05334-054
Figure 62. Operation in Controller Mode for Automatic Gain Control
Rev. 0 | Page 26 of 48
AD8364
CONSTANT OUTPUT POWER OPERATION
In controller mode, the AD8364 can be used to hold the output power stable over a broad temperature/input power range. This can be very useful in systems, such as a transmit module driving a high power amplifier (HPA) in a basestation, that connect multiple power sensitive modules together. In applications where stable output power is needed, the RF output is connected to Channel B using a coupler, VLVL is connected to VREF, VSTB is used to set the power to a particular level and can be controlled using a DAC or a dc voltage, OUTB is used to drive the gain control of an amplifier that is capable of negativegain law conformance (such as the AD8367), and ADJB (set at 0 V in this example) is used to control the temperature drift. Using this configuration, the RF input signal is down converted to 80 MHz using the AD8343 and amplified using the AD8367. The signal then splits and part of it is fed back to the AD8364 through Channel B, and a setpoint voltage is applied to VSTB. This voltage corresponds to a particular power level, which is determined by the slope of the AD8364. The power detected at the input of the AD8364 is compared with this voltage, and the voltage present at OUTB is adjusted up or down to match the setpoint voltage, with the power detected on the input. The OUTB voltage is connected to the gain control of the AD8367 VGA and increases or decreases the gain of the AD8367, resulting in the output power being held constant, regardless of variations in the input power. The AD8364 is able to maintain a fixed output power from the AD8367 even though its input power is changing. The input power can vary over a 36 dB range, while the output power remains constant and the drift over temperature is less than 0.2 dB Figure 64 shows a constant output power circuit using the AD8364 and the AD8367 VGA. The input power was swept from +3 dBm to -35 dBm, the output power was measured at multiple temperatures between -40C and +85C, and the power changed less than 0.07 dB (Figure 63).
-15.0 -15.1 -15.2 -15.3 POUT +25C
POUT +85C
POUT (dBm)
-15.4 -15.5 -15.6 -15.7 -15.8 -15.9 POUT -40C
-20C
-35
-30
-25
-20 -15 PIN (dBm)
-10
-5
0
5
Figure 63. AD8364 Constant Power Performance
Rev. 0 | Page 27 of 48
05334-033
-16.0 -40
AD8364
RFIN 1880MHz
AD8343 AD8367
0
0 107
IFOUT 80MHz
90MHz LPF MODE SEL 0V TO 1.2V VPOS
11dB COUPLING
R24 0 R23 0 C23 100pF R5 0 C8 0.1F C13 0.1F C12 100pF C14 0.1F
C11 0.1F R4 0 C9 0.1F C10 100pF T2 LDB181G8820C-110 C5 C7 0.1F 0.1F
1:4 R3 OPEN 27 PWDN J2 A 25 24 23
TEMP SENSOR J4
R6 0
C15 0.1F
22 21 20 19 18 17
CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA VPSA VSTA 16 R9 0
INPA J3
26
INHA
OUTA 15 R10 0
INLA
FBKA 14
SW1
B
C6 0.1F
28
AD8364ACPZ
PWDN OUTP 13
VPOS
R2 10k
29
COMR EXPOSED PADDLE
OUTN 12 R11 0
C4 0.1F
30 INPB J1 1:4 R1 OPEN
INLB
FBKB 11
C5 0.1F
C3 0.1F T1 ETK4-2T
31
INHB
OUTB 10 R12 0 R13 OPEN R14 OPEN VSTB 0.4V TO 3.4V
32
VPSB CHPB DECB COMB ADJB
1 2 3 4
VSTB 9 ADJA
5
R21 0
C20 100pF C21 0.1F
VREF
6
VLVL
7
CLPB
8
C22 0.1F
R20 0
R18 0 0.705V
C19 0.1F C18 OPEN R16 OPEN C17 0.1F R15 0 C16 0.1F
VPOS TP1 COMM TP2
C1 0.1F
C24 100pF
VREF
Figure 64. Constant Output Power Circuit
Rev. 0 | Page 28 of 48
05334-055
AD8364
GAIN-STABLE TRANSMITTER/RECEIVER
There are many applications for a transmitter or receiver with a highly accurate temperature-stable gain. For example, a multicarrier basestation high power amplifier (HPA) using digital predistortion has a power detector and an auxiliary receiver. The power detector and all parts associated with it can be removed if the auxiliary receiver has a highly accurate temperature-stable gain. With a set gain receiver, the ADC on the auxiliary receiver can not only determine the overall power being transmitted but can also determine the power in each carrier for a multicarrier HPA. In controller mode, the AD8364 can be used to hold the receiver gain constant over a broad input power/temperature range. In this application, the difference outputs are used to hold the receiver gain constant. The RF input is connected to INPA, using a 19.1 dB coupler, and the down converted output from our signal chain is connected to INPB, using a 10.78 dB coupler. A 0.1 F capacitor is connected between FBKA and OUTP, forming an integrator. OUTA is connected to VLVL, forcing OUTP to adjust the VGA so that OUTB is equal to OUTA. The circuit gain is set by the difference in the coupling values of the input and output couplers. As noted, OUTP is used to drive the gain control of the ADL5330 by adjusting the gain up or down as needed to force the power at the AD8364 inputs to be equal in amplitude. Since operating at different frequencies, the appropriate voltages on the ADJ[A, B] pins must be supplied. Because INPA is operating at 1880 MHz, ADJA is set to 0.75 V. Likewise, because INPB is operating at 80 MHz, ADJB is set to 0 V. Because the difference in the coupler values is 8.32 dB, a fixed gain of -8.32 dB is expected. In practice, there is a gain of -13 dB. This is caused by the intercept shift of the AD8364 due to its frequency response, the insertion loss of the output coupler, and the insertion loss differences of the baluns used on the input of the AD8364. In this configuration, approximately 33 dB of control range with 0.5 dB drift over temperature is obtained. Figure 66 shows a gain-stable receiver amplifier circuit using the AD8364 to control an ADL5330 VGA and the AD8343 mixer. The input power was swept from +3 dBm to -35 dBm, the output power was measured, and the gain was calculated at multiple temperatures between -40C and +85C. Note that the gain changed less than 0.45 dB over this range (Figure 65). Most of the gain change was caused by performance differences at different frequencies.
-11.0
-11.5
-12.0
-40C
GAIN (dB)
-12.5 +25C -13.0
+85C
-13.5
-35
-30
-25
-20 -15 PIN (dBm)
-10
-5
0
5
Figure 65. Performance of Gain-Stable Receiver
Rev. 0 | Page 29 of 48
05334-034
-14.0 -40
AD8364
RFIN 1880MHz 0 0
AD8343 ADL5330
0
0 107
IFOUT 80MHz
454 19dB COUPLING 90MHz LPF MODE SEL 0V TO 1.2V VPOS
11dB COUPLING
R24 0 R23 0 C23 100pF R5 0 C8 0.1F C13 0.1F C12 100pF C14 0.1F
C11 0.1F R4 0 C9 0.1F C10 100pF T2 LDB181G8820C-110 C5 C7 0.1F 0.1F
INPA J3 1:4 R3 OPEN 27 PWDN J2 A 25 24 23
TEMP SENSOR J4
R6 0
C15 0.1F
22 21 20 19 18 17
CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA VPSA VSTA 16 R9 0
26
INHA
OUTA 15 0.1F
INLA
FBKA 14
SW1
B
C6 0.1F
28
AD8364
PWDN OUTP 13
DIFF OUT +
VPOS
R2 10k
29
COMR
OUTN 12 R11 0
C4 0.1F
30 INPB J1 1:4 R1 OPEN
INLB
FBKB 11
C5 0.1F
C3 0.1F T1 ETK4-2T
31
INHB
OUTB 10 R12 0 R13 OPEN R14 OPEN
32
VPSB CHPB DECB COMB ADJB
1 2 3 4
VSTB 9 ADJA
5
R21 0
C20 100pF C21 0.1F
VREF
6
VLVL
7
CLPB
8
C22 0.1F
R20 0
R18 0 0.75V
C19 0.1F C18 OPEN R16 OPEN C17 0.1F R15 0 C16 0.1F
VPOS TP1 COMM TP2
C1 0.1F
C24 100pF
VREF
05334-056
Figure 66. Gain-Stable Receiver Circuit
Rev. 0 | Page 30 of 48
AD8364
TEMPERATURE COMPENSATION ADJUSTMENT
The AD8364 has a highly stable measurement output with respect to temperature. However, when the RF inputs exceed a frequency of 600 MHz, the output temperature drift must be compensated for using ADJ[A, B] for optimal performance. Proprietary techniques are used to compensate for the temperature drift. The absolute value of compensation varies with frequency, balun choice, and circuit board material. Table 5 shows recommended voltages for ADJ[A, B] to maintain a temperature drift error of typically 0.5 dB or better over the entire rated temperature range with the recommended baluns. Table 5. Recommended Voltages for ADJ[A, B]
Frequency (MHz) ADJ[A, B] (V) 450 0 880 0.5 1880 0.65 2140 0.85 2500 1.10
Figure 68 shows a simplified schematic representation of the ADJ[A, B] interface.
VPSR INTERNAL CURRENT
ADJ[A, B]
VREF/2
05334-036
COMR IADJ[A, B]
Figure 68. ADJ[A, B] Interface Simplified Schematic
DEVICE CALIBRATION AND ERROR CALCULATION
The measured transfer function of the AD8364 at 2.14 GHz is shown in Figure 69. The figure shows plots of both output voltage vs. input power and calculated error vs. input power. As the input power varies from -50 dBm to 0 dBm, the output voltage varies from 0.4 V to about 2.8 V.
VOUT (V)
ERROR CW +85C
1.70 +85C 1.65 +65C 1.60
1.75 1.40 1.05 0.70
0 -0.4 -0.8 -1.2 -1.6
VOUT2
VOUT1
OUTA (V)
+45C 1.55 +25C 1.50 +10C -20C 1.45 -40C 0 0.25 0.50 0.75 1.00 1.25 1.50 ADJA (V) 1.75 2.00 2.25 2.50
0.35 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN MEAS (dBm)
PIN1 PIN2
0
5
INTERCEPT
Figure 69. Transfer Function at 2.14 GHz.
05334-035
1.40
Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy. The equation for output voltage can be written as VOUT = Slope x (PIN - Intercept) Where Slope is the change in output voltage divided by the change in power (dB), and Intercept is the calculated power at which the output voltage would be 0 V. (Note that Intercept is a theoretical value; the output voltage can never achieve 0 V). In general, the calibration is performed by applying two known signal levels to the AD8364's input and measuring the corresponding output voltages. The calibration points are generally chosen to be within the linear-in-dB operating range of the device (see the Specifications section for more details).
Figure 67. OUTA vs. ADJA over Temp. Pin = -30 dBm, 1.9 GHz
The ADJ[A, B] input has high input impedance. The input can be conveniently driven from an attenuated value of VREF using a resistor divider, if desired.
Rev. 0 | Page 31 of 48
04862-037
-2.0 10
ERROR (dB)
Compensating the device for temperature drift using ADJ[A, B] allows for great flexibility. If the user requires minimum temperature drift at a given input power or subset of the dynamic range, the ADJ[A, B] voltage can be swept while monitoring OUT[A, B] over temperature. Figure 67 shows the result of such an exercise with a broadband balun, one that is not the recommended balun at 1880 MHz. The value of ADJ[A, B] where the output has minimum movement (approximately 0.77 V for the example in Figure 67) is the recommended voltage for ADJ[A, B] to achieve minimum temperature drift at a given power and frequency.
3.50 3.15
ERROR CW -40C BLUE = -40C GREEN = +25C RED = +85C
2.0 1.6 1.2
ERROR CW +25C
2.80 2.45 2.10
0.8 0.4
AD8364
Calculation of the slope and intercept is done using the equations: Slope = (VOUT1 - VOUT2)/(PIN1 - PIN2) Intercept = PIN1 - (VOUT1/Slope) Once slope and intercept have been calculated, an equation can be written that will allow calculation of the input power based on the output voltage of the detector. PIN (unknown) = (VOUT1(measured)/Slope) + Intercept The log conformance error of the calculated power is given by Error (dB) = (VOUT(MEASURED) - VOUT(IDEAL))/Slope Figure 69 includes a plot of the error at 25C, the temperature at which the log amp is calibrated. Note that the error is not zero. This is because the log amp does not perfectly follow the ideal VOUT vs. PIN equation, even within its operating region. The error at the calibration points (-43 dBm and -23 dBm in this case) will, however, be equal to zero by definition. Figure 69 also includes error plots for the output voltage at -40C and +85 C. These error plots are calculated using the slope and intercept at 25C. This is consistent with calibration in a mass-production environment, where calibration at temperature is not practical. Calibration points should be chosen to suit the application at hand. In general, though, do not choose calibration points in the nonlinear portion of the log amp's transfer function (above 0 dBm or below -50 dBm in this case). Figure 71 shows how calibration points can be adjusted to increase dynamic range, but at the expense of linearity. In this case, the calibration points for slope and intercept are set at -1 dBm and -50 dBm. These points are at the end of the device's linear range. At 25C, there is an error of 0 dB at the calibration points. Note also that the range over which the AD8364 maintains an error of <0.4 dB is extended to 57 dB at 25C. The disadvantage of this approach is that linearity suffers, especially at the top end of the input range. Another way of presenting the error function of a log amp detector is shown in Figure 72. In this case, the dB error at hot and cold temperatures is calculated with respect to the output voltage at ambient. This is a key difference in comparison to the previous plots, in which all errors have been calculated with respect to the ideal transfer function at ambient. When the alternative technique, the error at ambient becomes by definition equal to 0 (see Figure 72). This would be valid if the device transfer function perfectly followed the ideal VOUT = Slope x (PIN - Intercept) equation. However, since an rms amp, in practice, never perfectly follows this equation (especially outside of its linear operating range), this plot tends to artificially improve linearity and extend the dynamic range, unless enough calibration points were taken to remove the error. This plot is a useful tool for estimating temperature drift at a particular power level with respect to the (nonideal) output voltage at ambient.
SELECTING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE
In some applications, very high accuracy is required at one power level or over a reduced input range. For example, in a wireless transmitter, the accuracy of the high power amplifier (HPA) is most critical at or close to full power. Figure 70 shows the same measured data as Figure 69. Notice that accuracy is very high from -10 dBm to -25 dBm. At approximately -45 dBm, the error increases to about -0.3 dB because the calibration points have been changed to -15 dBm and -25 dBm.
Rev. 0 | Page 32 of 48
AD8364
3.50 3.15
VOUT (V)
BLUE = -40C GREEN = +25C RED = +85C ERROR CW -40C
2.0 1.6 1.2
ERROR CW +25C ERROR CW +85C
3.50 3.15 2.80 2.45
ERROR (dB)
2.0 ERROR CW -40C 1.6 1.2 0.8 ERROR CW +25C
2.80 2.45 2.10 1.75
0.8 0.4 0 -0.4 -0.8 -1.2
1.75 1.40 1.05 0.70 ERROR CW +85C
0 -0.4 -0.8 -1.2 -1.6
VOUT1
1.40 1.05 0.70 0.35 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 INTERCEPT PIN MEAS (dBm)
PIN1 PIN2
-1.6
0.35
0 5 10
04862-038
-2.0
0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN MEAS (dBm)
0
5
Figure 70. Output Voltage and Error vs. PIN with 2-Point Calibration at -15 dBm and -25 dBm, 2.14 GHz
Figure 72. Error vs. Temperature with Respect to Output Voltage at 25 C, 2.14 GHz (Does Not Account for Transfer Function Nonlinearities at 25C)
PIN1
PIN2
3.50 3.15 ERROR CW -40C 2.80 2.45 ERROR CW +25C 1.75 1.40 1.05 0.70
VOUT1
2.0 1.6 1.2 0.8
VOUT2
0 ERROR CW +85C -0.4 -0.8 -1.2 -1.6 -2.0 10
0.35 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN MEAS (dBm) 57dB DYNAMIC RANGE 0 5
ERROR (dB)
2.10
0.4
VOUT (V)
Figure 71. Dynamic Range Extension by Choosing Calibration Points that are Close to the End of the Linear Range, 2.14 GHz
Rev. 0 | Page 33 of 48
04862-039
04862-040
-2.0 10
ERROR (dB)
VOUT2
2.10
0.4
VOUT (V)
AD8364
COMA ACOM ACOM
18
CHPA
DECA
TEMP
VPSR
ALTERING THE SLOPE
None of the changes to operating conditions discussed so far affect the logarithmic slope, VSLOPE, in Equation 7. The slope can readily be altered by controlling the fraction of OUT[A, B] that is fed back to the setpoint interface at the VST[A, B] pin. When the full signal from OUT[A, B] is applied to VST[A, B], the slope assumes its nominal value of 50 mV/dB. It can be increased by including a voltage divider between these pins, as shown in Figure 73. Moderately low resistance values should be used to minimize scaling errors due to the approximately 70 k input resistance at the VST[A, B] pin. Keep in mind that this resistor string also loads the output, and it eventually reduces the load-driving capabilities if very low values are used. Equation 17 can be used to calculate the resistor values. R1 = R2' (SD/50 - 1) where: SD is the desired slope, expressed in mV/dB. R2' is the value of R2 in parallel with 70 k. For example, using R1 = 1.65 k and R2 = 1.69 k (R2' = 1.649 k), the nominal slope is increased to 100 mV/dB. This choice of scaling is useful when the output is applied to a digital voltmeter because the displayed number directly reads as a decibel quantity with only a decimal point shift. Operating at a high slope is useful when it is desired to measure a particular section of the input range in greater detail. A measurement range of 60 dB would correspond to a 6 V change in VOUT at this slope, exceeding the capacity of the AD8364's output stage when operating on a 5 V supply. This requires that the intercept is repositioned to place the desired input range section within a window corresponding to an output range of 0.1 V VOUT 4.8 V, a 47 dB range. Using the arrangement shown in Figure 74, an output of 0.4 V corresponds to the lower end of the desired range, and an output of 3.5 V corresponds to the upper limit with 3 dB of margin at each end of the range, nominally -32 dBm to -1 dBm with the intercept at -35.6 dBm. Note that R2 is connected to VREF rather than ground. R3 is needed to ensure that the AD8364's reference buffer is correctly loaded. When the slope is raised by some factor, the loop capacitor, CLP[A, B], should be raised by the same factor to ensure stability and to preserve a chosen averaging time. The slope can be lowered by placing a voltage divider after the output pin, following standard practice. (17)
24
23
22
21
20
19
17
TEMP VPSA 25 INHA 26 INLA
27
VGA CONTROL
ISIG2 ITGT2
CLPA
16 15 14 13 12 11 10
VSTA OUTA FBKA OUTP OUTN FBKB VOUT OUTB R1 VSTB R2
CHANNEL A TruPwrTM
PWDN 28 COMR 29 INLB 30 INHB 31 VPSB 32
OUTA OUTB
CHANNEL B TruPwrTM
ISIG2 ITGT2 VGA CONTROL
4 5 6 7 8
9
BIAS
1 2 3
VLVL
Figure 73. External Network to Raise Slope
COMA
ACOM
ACOM
CHPA
DECA
TEMP
VPSR
24
23
22
21
20
19
18
17
TEMP VPSA 25 INHA 26 INLA 27 PWDN 28 COMR 29 INLB 30 INHB 31 VPSB 32 BIAS
1 2 3
VGA CONTROL
ISIG2 ITGT2
CLPA
16 VSTA 15 OUTA 14 FBKA 13 OUTP 12 OUTN 11 FBKB 10 9
CHANNEL A TruPwrTM
OUTA OUTB
CHANNEL B TruPwrTM
ISIG2 ITGT2 VGA CONTROL
4 5 6 7 8
OUTB VSTB
VOUT R1 4.02k R2 4.32k
COMB
VREF
VLVL
CHPB
DECB
CLPB
ADJB
ADJA
Figure 74. Scheme Providing 100 mV/dB Slope for Operation over a 3 mV to 300 mV Input Range
Rev. 0 | Page 34 of 48
05334-042
R3 2k
05334-041
COMB
VREF
CHPB
DECB
CLPB
ADJB
ADJA
AD8364
CHANNEL ISOLATION
Isolation must be considered when using both channels of the AD8364 at the same time. The two isolation requirements that should be considered are the isolation from one RF channel input to the other RF channel input and the isolation from one RF channel input to the other channel output. When using both channels of the AD8364, care should be taken in the layout to isolate the RF inputs from each other. Coupling on the PC board affects both types of isolation. In most applications, the designer has the ability to adjust the power going into the AD8364 through the use of different valued temperature-stable couplers and accurate temperaturestable attenuators. When isolation is a concern, it is useful to adjust the input power so the lowest expected detectable power is not far from the lowest detectable power of the AD8364 at the frequency of operation. The AD8364's lowest detectable power point has little variation from part to part and is not affected by the balun. This equalizes the signals on both channels at their lowest possible power level, which reduces the overall isolation requirements and possibly adds attenuators to the RF inputs of the device, reducing the RF channel input isolation requirements. Measuring the RF channel input to the other RF channel input isolation is straight forward, and the result of such an exercise is shown in Figure 75. Note that adding an attenuator in series with the RF signal increases the channel input-to-input isolation by the value of the attenuator. The isolation between one RF channel input and the other channel output is a little more complicated. Do not assume that worst-case isolation happens when one RF channel has high power and the other RF channel is set at its lowest detectable power. Worst-case isolation happens when the low power channel is at a nominally low power level, as chosen in Figure 76. If the inputs to both RF channels are at the same frequency, the isolation also depends on the phase shift between the RF signals put into the AD8364. This can be seen by placing a high power signal on one RF channel input and another signal (low power) slightly offset in frequency to the other RF channel. If the output of the low power channel is observed with an oscilloscope, it would have a ripple that would look similar to a full-wave rectified sine wave with a frequency equal to the frequency difference between the two channels, that is, a beat tone. The magnitude of the ripple reflects the isolation at a specific phase offset (note that two signals of slightly different frequencies act like two signals with a constantly changing phase), and the frequency of that ripple is directly related to the frequency offset. The data taken in Figure 76 assumes worst-case amplitude and phase offset. If the RF signals on Channel A and Channel B are at significantly different frequencies, the input-to-output isolation increase, depending on the capacitors placed on CLP[A, B] and CHP[A, B] and the frequency offset of the two signals (Figure 77), due to the response roll-off within AD8364.
-40 -45 -50 -55
ISOLATION (dB)
-60 B->A -65 -70 -75 A->B -80 -85
05334-021 05334-022
-90 10
100 1,000 FREQUENCY (MHz)
10,000
Figure 75. RF Channel Input-to-Input Isolation
16
PEAK INTERFERENCE (IN dB) TO A -45dBm INPUT SIGNAL DUE TO AN INTERFERING SIGNAL ON THE OTHER CHANNEL A INPUT B->A = B INTERFERING WITH A, X-AXIS IS CHANNEL B INPUT FREQUENCY SEPARATION OF THE TWO CHANNELS = 1kHz. SEE CHARACTERIZATION DESCRIPTION SECTION FOR MORE INFORMATION.
14 CHANNEL. A->B = A INTERFERING WITH B, X-AXIS IS
PEAK DEVIATION FROM -45dBm EQUIVALENT OUTPUTS (dB)
12 10 8 6 4 2
A->B 880MHz B->A 1880MHz A->B 1880MHz B->A 2140MHz B->A 2500 MHz A->B 2140MHz A->B 2500MHZ A->B 450 MHz B->A 450 MHz B->A 880MHz
0 -20
-15 -10 -5 0 5 10 INTERFERING CHANNEL AMPLITUDE (dBm)
15
Figure 76. Apparent Measurement Error Due to Overall Channel-to-Channel Cross-Coupling
PEAK DEVIATION FROM -45dBm EQUIVALENT OUTPUT(dB)
7 6 5 4 3 2 1 0 -20 PEAK INTERFERENCE (IN dB) TO A -45dBm INPUT SIGNAL DUE TO AN INTERFERING SIGNAL ON THE OTHER CHANNEL. A->B = A INTERFERING WITH B, X-AXIS IS CHANNEL A INPUT Freq chA = 2500 MHz Freq CHB = 1880MHz B->A = B INTERFERING WITH A, X-AXIS IS CHANNEL B INPUT Freq CHB = 2500 MHz Freq CHA = 1880 MHz FREQUENCY SEPARATION OF THE TWO CHANNELS = 620 MHz. SEE CHARCTERIZATION DESCRIPTION SECTION FOR MORE INFORMATION B->A A->B -15 -10 -5 0 5 10 15
05334-085
INTERFERING CHANNEL AMPLITUDE (dBm)
Figure 77. Improved Measurement Error with Increased Frequency Separation
Rev. 0 | Page 35 of 48
AD8364
CHOOSING THE RIGHT VALUE FOR CHP[A, B] AND CLP[A, B]
The AD8364's VGA includes an offset cancellation loop, which introduces a high-pass filter effect in its transfer function. The corner frequency, fHP, of this filter must be below that of the lowest input signal in the desired measurement bandwidth frequency to properly measure the amplitude of the input signal. The required value of the external capacitor is given by CHP[A, B] = 200 F/(2 x x fHP )(fHP in Hz) (18) Once the response time is set so that the AD8364 is just able to follow the RF burst requirements (within the tolerance of the capacitors), the output of the AD8364 should be evaluated with an oscilloscope. If there is ripple on the output (due to the modulated signal), averaging may need to be performed on the DSP to achieve a true rms response. Figure 44 and Figure 45 may help in determining the proper CLP[A, B] values to use.
SINGLE-ENDED INPUT OPERATION
For optimum operation, the RF inputs to the AD8364 should be driven differentially. However, the AD8364 RF inputs can also be driven in a single-ended configuration with reduced dynamic range. Figure 78 shows a recommended input configuration for a single channel. Figure 79 shows the performance obtained with the configuration shown in Figure 78. The user should note that the dynamic range performance suffers in single-ended configuration due to the inherent amplitude and phase imbalance at the RF inputs. However, at low frequency the dynamic range is quite good and users trying to detect low frequency or baseband signals may want to consider this as an option. At frequencies greater than 450 MHz, the dynamic range decreases to about 20 dB, reducing the AD8364's usefulness for many applications. Performance in single-ended configuration is subject to circuit board layout (see the Printed Circuit Board Considerations section).
INHx
Thus, for operation at frequencies down to 100 kHz, CHP[A, B] should be 318 pF. In the standard connections for the measurement mode, the VST[A, B] pin is tied to OUT[A, B]. For small changes in input amplitude (a few decibels), the time-domain response of this loop is essentially linear with a 3 dB low-pass corner frequency of nominally fLP = 1/(2 x x CLP[A, B] x 1.1 k). Internal time delays around this local loop set the minimum recommended value of this capacitor to about 300 pF, making fLP = 482 kHz. For operation at lower signal frequencies, or whenever the averaging time needs to be longer, use CLP[A, B] = 900 F/2 x x fLP (fLP in Hz) (19)
RF BURST RESPONSE TIME
RF burst response time is important for modulated signals that have large steps in power, such as a single carrier EVDO that has the potential for a greater than 20 dB burst of power (for approximately 200 s out of every 800 s). Accurate power detection for signals with RF bursts is achieved when the AD8364 is able to respond quickly to the change in RF power; however, the response time is limited by the capacitors placed on Pins CLP[A, B], CHP[A, B], and DEC[A, B]. Capacitors placed on the DEC[A, B] pins affect the response time the least and should be chosen as stated in the RF Input Interface section. Capacitors placed on CHP[A, B] and CLP[A, B] should be chosen according to the equations in the Choosing the Right Value for CHP[A, B] and CLP[A, B] section and the response time for the AD8364 should be evaluated. If the response time is not fast enough to follow the burst response, the values for CLP[A, B] should be decreased. The capacitor values placed on the CLP[A, B] have the largest effect on the rise and fall times. The capacitor values placed on CHP[A, B] affect the rising and falling corner of the response (overshoot or under-shoot); however, the falling corner is most likely swamped out by the effect of CLP[A, B].
Figure 78. Recommended Input Configuration for Single-Ended Input Drive
5.0 50MHz 4.5 4.0 3.5 3.0 50MHz Error
450MHz ERROR 100MHz
05334-044
When the input signal exhibits large crest factors, such as a WCDMA signal, CLP[A, B] must be much larger than might at first seem necessary. This is due to the presence of significant low frequency components in the complex, pseudo random modulation, which generates fluctuations in the output of the AD8364.
100 100
INLx
2.5 2.0 1.5 1.0 0.5 0 -60 -50 -40 -30 -20 -10 RF INPUT (dBm) 100MHz ERROR 0 10 20 45 MHz
ERROR (dB)
05334-045
OUTA (V)
Figure 79. Single-Ended Performance for the Configuration Shown in Figure 78
Rev. 0 | Page 36 of 48
AD8364
PRINTED CIRCUIT BOARD CONSIDERATIONS
Each RF input pin of the AD8364 presents 100 impedance relative to their respective ac grounds. To ensure that signal integrity is not seriously impaired by the printed circuit board (PCB), the relevant connection traces should provide appropriate characteristic impedance to the ground plane. This can be achieved through proper layout. When laying out an RF trace with controlled impedance, consider the following: * When calculating the RF line impedance, take into account the spacing between the RF trace and the ground on the same layer. Ensure that the width of the microstrip line is constant and that there are as few discontinuities, such as component pads, as possible along the length of the line. Width variations cause impedance discontinuities in the line and may result in unwanted reflections. Do not use silkscreen over the signal line because it can alter the line impedance. Keep the length of the RF input traces as short as possible. The accurate measurement range (that is, the dynamic range) of AD8364's detectors is sensitive to amplitude and phase matching of the signals presented at the differential inputs. Care should be taken to ensure matching of these parameters and to minimize parasitic capacitance on the RF inputs when laying out the PC board. It is also suggested that the two traces associated with each differential input be mirror images, or duplicates, of one another where possible. A high quality balun with known output magnitude and phase characteristics is recommended to perform single-ended to balanced conversions. It is possible to improve the dynamic range by skewing the amplitude and phase matching at the input. See the Typical Performance Characteristics section for more details. Stable, low ESR capacitors are mandatory in the RF circuitry of the AD8364. This corresponds to capacitors connected to Pins INH[A, B], INL[A, B], DEC[A, B], and CHP[A, B]. High ESR capacitors may result in amplitude and phase mismatch at the differential inputs, which in turn results in low dynamic range. Capacitors with poor aging characteristics under temperature cycling have been shown to accentuate the temperature drift during operation of the AD8364. Use of Samsung CL10 series multilayer ceramic capacitors (or similar) in the RF area are recommended. High transient and noise levels on the power supply, ground, and inputs should be avoided. This reinforces the need for proper supply bypassing and decoupling. See the Evaluation Boards for suggestions. A solder appropriate for either the lead-free or leaded version of the AD8364 should be chosen. After the circuit board has been soldered, it is important to thoroughly clean all excess solder flux and residues from the board. Any residual material may act as stray parasitic capacitance, which could result in degraded performance.
*
* *
Figure 80 shows the cross section of a PC board, and Table 6 shows two possible sets of dimensions that provide a 100 line impedance for FR-4 board material with r = 4.6 and Rodgers 4003 board material with r = 3.38. Table 6. Possible Trace Dimensions for ZO = 100
Dimension W H T
3W
FR-4 (mil) 22 53 2
W 3W
Rodgers 4003 (mil) 6 11 0.7
T
PACKAGE CONSIDERATIONS
H ER
05334-046
Figure 80. Cross-Section View of a PC Board
It is possible to approximate a 100 trace on a board designed with the 50 dimensions above by removing the ground plane within three line widths of the area directly below the trace. However, more predictable performance may be obtained with precise ground plane spacing. It is possible to design a circuit board with two ground planes, one plane for areas with 50 characteristic impedance and another for areas with 100 characteristic impedance. If the 100 plane is placed below the 50 plane, then an opening can be made in the 50 plane to allow the 100 traces to work against the 100 ground plane. The two ground planes should be connected together with as many vias as possible.
The AD8364 uses a compact 32-lead LFCSP. A large exposed paddle on the bottom of the device provides both a thermal benefit and a low inductance path to ground for the circuit. To make proper use of this packaging feature, the PCB RF/dc common ground reference needs to make contact directly under the device with as many vias as possible to lower the inductance and thermal impedance.
Rev. 0 | Page 37 of 48
AD8364
DESCRIPTION OF CHARACTERIZATION
The general hardware configuration used for most of the AD8362 characterization is shown in Figure 81. The signal sources used in this example are the Rohde & Schwarz SMIQ03B and Agilent E4438C. Input-matching baluns are used to transform the single-ended RF signal to its differential form. Due to the differential inputs' sensitivity to amplitude and phase mismatch, specific baluns were used for each characterization frequency to achieve the best performance. Other selected configurations are shown in Figure 82 and Figure 83 as well.
SIGNAL SOURCE -3dB INA OUTA OUTB OUTP CHARACTERIZATION OUTN BOARD VREF INB TEMP
BASIS FOR ERROR CALCULATIONS
The slope and intercept are derived using the coefficients of a linear regression performed on data collected in its central operating range. Error is stated in two forms: (1) error from linear response to CW waveform and (2) output delta from 25C performance. The error from linear response to CW waveform is the decibel difference in output from the ideal output defined by the conversions gain and output reference. This is a measure of the linearity of the device response to both CW and modulated waveforms. The error in dB is calculated by Error (dB) =
VOUT - Slope x (PIN - PZ ) Slope
AD8364
SIGNAL SOURCE
-3dB
AGILENT 34970A METER/ SWITCHING
where PZ is the x-axis intercept expressed in dBm. This is analogous to the input amplitude that would produce an output of 0 V, if such an output was possible. Error from the linear response to the CW waveform is not a measure of absolute accuracy, since it is calculated using the slope and intercept of each device. However, it verifies the linearity and the effect of modulation on the device's response. Similarly, error from 25C performance uses the 25C performance of a given device and waveform type as the reference from which all other performance parameters shown alongside it are compared. It is predominantly (and most often) used as a measurement of output variation with temperature.
05334-052
Figure 81. General Characterization Configuration
MINI-CIRCUITS ZHL-42W AD8340 OR AD8341 VECTOR MODULATOR
-6dB SPLITTER AGILENT 8648 RF SOURCE 50 -8dB
INHA/B -8dB -6dB
INLA/B -9dB -8dB -6dB
Figure 82. Configuration for Amplitude and Phase Mismatch Characterization
Rev. 0 | Page 38 of 48
05334-047
COMPUTER CONTROLLER
AD8364
VPOS R24 0 VPOS C23 100pF R5 0 C8 0.1F C13 0.1F C12 100pF C15 CLPA
24 23 22 21 20 19 18 17
TEKTDS510 SCOPE
C11 0.1F R4 0 C9 0.1F C10 100pF
25
CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA VPSA INHA INLA VSTA 16 OUTA 15 FBKA 14
SMIQ06B SIGNAL GENERATOR
26
3dB
BALUN
27
AD8364ACPZ
28
PWDN COMR INLB INHB VPSB
OUTP 13 OUTN 12 FBKB 11 OUTB 10 VSTB 9
LECROY9213 PULSE GENERATOR
29
30
BALUN
31
32
HP6236B POWER SUPPLY
R21 0
C20 100pF C21 0.1F
CHPB DECB COMB ADJB ADJA VREF VLVL CLPB
1 2 3 4 5 6 7 8
C22 0.1F
C16 CLPB
VPOS
Figure 83. Configuration for RF Burst Measurement
Rev. 0 | Page 39 of 48
05334-048
C1 0.1F
C24 100pF
AD8364
EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS
There are two evaluation boards for the AD8364, one appropriate for low frequency work (AD8364-EVAL-500) and another one designed for use at 2140 MHz (AD8364-EVAL2140). Each board has a balun specific to operation in the designated frequency range. The RF area layout of the circuit board used for characterization work at 880 MHz is included in this section, showing the footprint of the recommended balun (Mini-Circuits JTX-4-10T) and trace lengths used. The user may obtain different performance than shown in this data sheet if their layout dimensions and style differ.
Figure 84. AD8364-EVAL-500 Evaluation Board RF Area Layout
Rev. 0 | Page 40 of 48
05334-092
AD8364
Figure 85. AD8364_EVAL-2140 Evaluation Board RF Area Layout
Figure 86. 880 MHz Characterization Board RF Area Layout
Rev. 0 | Page 41 of 48
05334-050
05334-093
AD8364
Table 7. AD8364-EVAL-500 Evaluation Board Configuration Options (10 MHz to 650 MHz)
Component T1, T2 Function/Notes The dynamic range of the AD8364 is directly related to the magnitude and phase balance of the balun feeding the RF signal to the part. The evaluation board includes M/A-COM ETK4-2T soldered to the board and two unsoldered M/A-COM ETC1.6-4-2-3. The ETK4-2T has good magnitude and phase balance between 10 MHz and 650 MHz, but slowly degrades above 650 MHz due to the balun. The M/A-COM ETC1.6-4-2-3 broadband baluns allow limited dynamic range performance between 500 MHz and 2500 MHz. Better dynamic range can be achieved by using narrow band baluns with better magnitude and phase performance. Supply filtering/decoupling capacitors. Supply filtering/decoupling capacitors. VREF filtering/decoupling capacitor. Optional VLVL filtering/decoupling capacitor. Output low-pass filter capacitors (CLPA/B). Output low-pass filter capacitors, which can be activated by removing jumpers R6 and R15. Input bias-point decoupling capacitors (DECA/B). Input bias-point decoupling capacitors (DECA/B). Stable, low ESR capacitors are mandatory in the RF input area of the AD8364. This corresponds to capacitors connected to Pins INH[A, B], INL[A, B], DEC[A, B], and CHP[A, B]. Poor quality capacitors may result in amplitude and phase mismatch at the differential inputs, which in turn results in low dynamic range. Capacitors with poor aging characteristics under temperature cycling have been shown to accentuate the temperature drift during operation of the AD8364. Using Samsung CL10 series multilayer ceramic capacitors (or similar) in the RF area is suggested. Input high-pass filter capacitor (CHPA/B). R17/R19 are usually jumpers and R18/R20 are usually left open. The pads for R17/R18 or R19/R20 can be used to make voltage dividers to set the ADJA/B voltages for temperature compensation at different frequencies. R12 is usually a jumper and R13 is usually open, but the pads can also be used to make a voltage divider to adjust the slope of Channel B. AD8364. Jumpers. Capacitors can be installed for controller mode. Optional pull-down resistors. 100 resistor to be added when input coupling from a singleended source (not installed). To be added for use in slope adjustment (not installed). Power-down/enable or external power-down selector, open is enable (Position A, unloaded). Measurement mode (Position A)/controller mode (Position B) selector. VLVL VREF (Position A)/external control (Position B) selector. ADJA VREF (Position A)/external control (Position B) selector. ADJB VREF (Position B)/external control (Position A) selector. Part Number M/A-COM ETK4-2T Default Value
C11, C13, C21 C10, C12, C20 C19 C18 C15, C17 C14, C16 C23, C24 C1, C8 C2, C3, C4, C5, C6, C7
0.1 F 100 pF 0.1 F OPEN 0.1 F 0.1 F Samsung CL10B101KONC Samsung CL10B104KONC Samsung CL10B104KONC 100 pF 0.1 F 0.1 F
C9, C22 R17, R18, R19, R20
Samsung CL10B104KONC
0.1 F R17/R19 = 0 R18/R20 = OPEN R12 = 0 R13 = OPEN
R12, R13
DUT R4, R5, R6, R9, R15, R21, R24, R23 R10, R11 R2, R16 R1, R3 R14 SW1 SW2, SW3 SW4 SW5 SW6
AD8364ACPZ 0 0 10 k/OPEN OPEN/100 OPEN
Rev. 0 | Page 42 of 48
AD8364
Table 7. AD8364-EVAL-2140 Evaluation Board Configuration Options (2140 MHz)
Component T1, T2 Function/Notes The dynamic range of the AD8364 is directly related to the magnitude and phase balance of the balun feeding the RF signal to the part. At 2140 MHz, we have found it necessary to use a narrow band balun and have used the Murata LDB212G1020C-001. Supply filtering/decoupling capacitors. Supply filtering/decoupling capacitors. VREF filtering/decoupling capacitor. Optional VLVL filtering/decoupling capacitor. Output low-pass filter capacitors (CLPA/B). Output low-pass filter capacitors, which can be activated by removing jumpers R6 and R15. Input bias-point decoupling capacitors (DECA/B). Input bias-point decoupling capacitors (DECA/B). Stable, low ESR capacitors are mandatory in the RF input area of the AD8364. This corresponds to capacitors connected to Pins INH[A, B], INL[A, B], DEC[A, B], and CHP[A, B]. Poor quality capacitors may result in amplitude and phase mismatch at the differential inputs, which in turn results in low dynamic range. Capacitors with poor aging characteristics under temperature cycling have been shown to accentuate the temperature drift during operation of the AD8364. Using Samsung CL10 series multilayer ceramic capacitors (or similar) in the RF area is suggested. Input high-pass filter capacitor (CHPA/B). R17/R19 are usually jumpers and R18/R20 are usually left open. The pads for R17/R18 or R19/R20 can be used to make voltage dividers to set the ADJA/B voltages for temperature compensation at different frequencies. AD8364. Jumpers. Capacitors can be installed for controller mode. Optional loading resistor for TEMP. Optional pull-down resistors. To be added for use in slope adjustment (not installed). Power-down/enable or external power-down selector, open is enable (Position A, unloaded). Measurement mode (Position A)/controller mode (Position B) selector. VLVL VREF (Position A)/external control (Position B) selector. ADJA VREF (Position A)/external control (Position B)l selector. ADJB VREF (Position B)/external control (Position A) selector. Part Number Murata LDB212G1020C-00 Default Value
C11, C13, C21 C10, C12, C20 C19 C18 C15, C17 C14, C16 C23, C24 C1, C8 C2, C3, C4, C5, C6, C7
0.1 F 100 pF 0.1 F OPEN 0.1 F 0.1 F Samsung CL10B101KONC Samsung CL10B104KONC Samsung CL10B104KONC 100 pF 0.1 F 0.1 F
C9, C22 R17, R18, R19, R20
Samsung CL10B104KONC
0.1 F R17/R19 = 0 R18/R20 = OPEN
DUT R4, R5, R6, R9, R12, R15, R21 R10, R11 R24 R2, R16 R14, R27 SW1 SW2, SW3 SW4 SW5 SW6
AD8364ACPZ 0 0 1 k OPEN OPEN
Rev. 0 | Page 43 of 48
AD8364 EVALUATION BOARDS
VPOS R24 0 R23 0 C23 100pF R5 0 C8 0.1F C13 0.1F C12 100pF C14 0.1F
C11 0.1F R4 0 C9 0.1F C10 100pF
25 24 23
TEMP SENSOR J4
R6 0
C15 0.1F
22 21 20 19 18 17
CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA VPSA VSTA 16 R9 0
SW2 B
A
SETPOINT VOLTAGE A J5
C5 0.1F
INPA J3 1:4
T2 ETK4-2T
C7 0.1F
26 R3 OPEN 27
INHA
OUTA 15 R10 0
OUTPUT VOLTAGE A J6
INLA
FBKA 14
PWDN J2
A
SW1
B
C6 0.1F
28
AD8364ACPZ
PWDN OUTP 13
VPOS
R2 10k
29
DIFF OUT + J7 DIFF OUT + J8 R11 0
COMR EXPOSED PADDLE
OUTN 12
C4 0.1F
1:4 INPB J1 R1 OPEN
30
INLB
FBKB 11
C2 0.1F
T1 ETK4-2T
C3 0.1F
31
INHB
OUTB 10 R12 0 R13 OPEN R14 OPEN
A
OUTPUT VOLTAGE B J9
32
VPSB CHPB DECB COMB ADJB
1 2 3 4
VSTB 9 ADJA
5
R21 0
C20 100pF C21 0.1F C1 0.1F
VREF
6
VLVL
7
CLPB
8
SW3 B
SETPOINT VOLTAGE B J10
C22 0.1F
R20 R18 OPEN OPEN
C19 0.1F C18 OPEN C17 0.1F R15 0 C16 0.1F
VPOS TP1 COMM TP2
C24 100pF
R19 0 SW6
A B
R17 0 SW5
B A
R16 OPEN
SW4
A B
VREF
ADJB J13
ADJA J12
REF LEVEL VOLTAGE J11
Figure 87. AD8364-EVA-500 Evaluation Board
Rev. 0 | Page 44 of 48
05334-051
AD8364
VPOS
C23 100pF
R5 0 C8 0.1F
C13 0.1F C12 100pF R24 1k
C14 0.1F
C11 0.1F R4 0 C9 0.1F C10 100pF T2 C5 LDB212G1020C C7 0.1F 0.1F
1:4 R3 OPEN 27 PWDN J2 A 25 24 23
TEMP SENSOR J4
R6 0 VREF C15 0.1F
22
21
20
19
18
17
CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA VPSA VSTA 16
R27 OPEN SW2 B R9 0
A
SETPOINT VOLTAGE A J5
INPA J3
26
INHA
OUTA 15 R10 0
OUTPUT VOLTAGE A J6
INLA
FBKA 14
SW1
B
C6 0.1F
28
AD8364ACPZ
PWDN OUTP 13
DIFF OUT + J7 DIFF OUT - J8 R11 0
VPOS C4 0.1F
1:4 INPB J1
29
COMR EXPOSED PADDLE
OUTN 12
30
INLB
FBKB 11
C2 0.1F T1 LDB212G1020C
C3 0.1F
31
INHB
OUTB 10 R12 0 R14 OPEN VREF C17 0.1F R15 0 C16 0.1F
A
OUTPUT VOLTAGE B J9
32
VPSB CHPB DECB COMB ADJB
1 2 3 4
VSTB 9 ADJA
5
R21 0
C20 100pF C21 0.1F C1 0.1F
VREF
6
VLVL
7
CLPB
8
SW3 B
SETPOINT VOLTAGE B J10
C22 0.1F
R20 R18 OPEN OPEN
C19 0.1F C18 OPEN
VPOS TP1 COMM TP2
C24 100pF
R19 0 SW6
B A
R17 0 SW5
B A
R16 OPEN
SW4
A B
VREF
ADJB J13
ADJA J12
REF LEVEL VOLTAGE J11
Figure 88. AD8364-EVAL-2140 Evaluation Board
Rev. 0 | Page 45 of 48
05334-097
AD8364
ASSEMBLY DRAWINGS
Figure 89. AD8364-EVAL-500 Assembly Drawing
05334-096
Figure 90. AD8364-EVAL-2140 Assembly Drawing
Rev. 0 | Page 46 of 48
05334-098
AD8364 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
3.45 3.30 SQ 3.15
8
0.50 0.40 0.30
17 16
9
0.25 MIN 3.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 91. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8364ACPZ-WP1, 2 AD8364ACPZ-REEL71 AD8364ACPZ-RL21 AD8364ACP-REEL7 AD8364-EVAL-500 AD8364-EVAL-2140
1 2
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board, Low Frequency to 500 MHz Evaluation Board, 2140 MHz only
Package Option CP-32-3 CP-32-3 CP-32-3 CP-32-3
Ordering Quantity 36 Units 1,500 Units 250 Units 1,500 Units
Z = Pb-free part. WP = Waffle Pack
Rev. 0 | Page 47 of 48
AD8364 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05334-0-4/05(0)
Rev. 0 | Page 48 of 48

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